An All-Digital, Cyclic and Synthesizable TDC in the ADPLL-Based Clocking Digital Systems for Multidomain Power Management

Shao Hua Chen; Ming Bo Lin

doi:10.4028/www.scientific.net/AMM.597.515

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 597An All-Digital, Cyclic and Synthesizable TDC in...

An All-Digital, Cyclic and Synthesizable TDC in the ADPLL-Based Clocking Digital Systems for Multidomain Power Management

Abstract:

In this paper, we propose an all-digital, cyclic and synthesizable TDC architecture, which may be used as a core block in ADPLLs to replace the analog block as a phase/frequency detector and a charge pump. Traditional designs of the DVFS scheme for multidomain power management are based on a conventional analog PLL to generate the dynamic voltage and frequency in which the use of a digital TDC eliminates the need for current sources in conventional analog PLLs.

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Periodical:

Applied Mechanics and Materials (Volume 597)

Pages:

515-518

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.597.515

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Online since:

July 2014

Authors:

Shao Hua Chen*, Ming Bo Lin

Keywords:

All-Digital Phase-Locked Loop (ADPLL), Dynamic Voltage Frequency Scaling (DVFS), System-on-Chip (SoC), Time-To-Digital Converter (TDC)

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References

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