Digital Design of a BCD Multiplication Scheme

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This paper presents a new scheme for BCD multiplication. This new scheme features a completely carry-free multiplication. The parallel structure of the new algorithm is investigated. This fast architecture was derived by looking at multiplication in a fresh perspective. A carry is able to be computed without performing multiplication on any of the previous bits. The new approach is expected to have a lot of potential contributions to digital design.

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90-93

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June 2011

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© 2011 Trans Tech Publications Ltd. All Rights Reserved

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