A Low Power Reference Buffer Used in High-Speed High-Precision Pipelined ADC

Ming Yuan Xu; Shui Qin Yao; Liang Li; Xing Fa Huang; Xiao Feng Shen; Xi Chen

doi:10.4028/www.scientific.net/AMM.667.379

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 667A Low Power Reference Buffer Used in High-Speed...

A Low Power Reference Buffer Used in High-Speed High-Precision Pipelined ADC

Abstract:

An analysis of the output impedance of the reference buffer for pipelined ADC is presented is this paper. To achieve high performance of the reference buffer, damping network has added in. The output impedance of buffer amplifier is made equal to the resistance of the damping network. As a result, the effective impedance is made independent of frequency. Spectre simulation with 14-bit 250MSPS pipelined ADC loads, the results show the settling time can be achieved 1.2 ns with 0.0023% precision, and the noise floor per bin is-114dB with the power consumption is 42.3mW. The reference buffer can meet the requirement of 14-bit up to 800MSPS pipelined ADC.

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Periodical:

Applied Mechanics and Materials (Volume 667)

Pages:

379-382

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.667.379

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Online since:

October 2014

Authors:

Ming Yuan Xu*, Shui Qin Yao, Liang Li, Xing Fa Huang, Xiao Feng Shen, Xi Chen

Keywords:

Faster Settling, Low Power, Pipelined ADC, Reference Buffer

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* - Corresponding Author

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