Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library

L. Gurusamy; Muhammad Kashif; Norhuzaimin bin Julai

doi:10.4028/www.scientific.net/AMM.833.149

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Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library
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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 833Design and Implementation of an Efficient Hybrid...

Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library

Abstract:

This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction in comparison of the traditional Carry Look-Ahead Adder (CLA).

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Periodical:

Applied Mechanics and Materials (Volume 833)

Pages:

149-156

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.833.149

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Online since:

April 2016

Authors:

L. Gurusamy, Muhammad Kashif, Norhuzaimin bin Julai

Keywords:

Carry Select Adder (CSEA), Hybrid Parallel-Prefix Adder (HPA), Ling’s Algorithm, Parallel-Prefix Adder, Verilog Hardware Descriptive Language (HDL)

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