Soft Error Mitigation on Dual Rail Latch

Article Preview

Abstract:

A single event upset (SEU) or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption. With increasing system complexities and integration scale, transistors have become more vulnerable to soft error, necessitating analysis of soft error in circuits, which is the focus of this thesis. Vulnerability of circuits to soft errors is further aggravated by several factors, such as variations in the process and temperatures. Process variations are inaccuracies in the manufacturing process which may lead to deterioration of circuit performance and increase in power consumption. Temperature variation degrades the threshold voltage, carrier mobility and velocity saturation of transistor. As a result of degrading carrier mobility, the drain current becomes lower thus increasing the sensitivity of the node to SEU.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

119-125

Citation:

Online since:

April 2016

Keywords:

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2016 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] International Technology Roadmap for Semiconductors (www. itrs. net).

Google Scholar

[2] Borkar, S, Thousand Core Chips: A Technology Perspective, Proceedings of the 44th annual Design Automation Conference. ACM: San Diego, California, (2007).

DOI: 10.1145/1278480.1278667

Google Scholar

[3] NASA Thesaurus.

Google Scholar

[4] VideogeniX, SEUs and Their Effects on Electronic Devices: A White Paper on Why Electronic Equipment Locks Up for No Apparent Reason and How to Remedy the Situation, (2006).

Google Scholar

[5] Subahasish Mitra, Ming Zhang, Norbert Seifert, TM Mak and Kee Sup Kim, Soft Error Resilient System Design through Error Correction, International Conference on Very Large Scale Integration, IFIP, 2006M. Young, The Techincal Writers Handbook. Mill Valley, CA: University Science, (1989).

DOI: 10.1109/vlsisoc.2006.313256

Google Scholar

[6] Fan Wang and Vishwani D. Agrawal, Single Event Upset: An Embedded Tutorial, 21st International Conference on VLSI Design, 2008, p.429 – 434.

DOI: 10.1109/vlsi.2008.28

Google Scholar

[7] Anghel, M. Rebaunger, M. Sonze Reorda and M. Violante, Multi-Level Fault Effects Evaluation, Radiation Effects on Embedded Systems, Springer, 2007, pp.69-88.

DOI: 10.1007/978-1-4020-5646-8_4

Google Scholar

[8] Gottfried Fuchs, Matthias Fugger and Andreas Steininger, On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme, Fault-Tolerant Distributed Algorithms on VLSI Chips.

DOI: 10.1109/async.2009.15

Google Scholar

[9] Mitra, S., N. Seifert, M. Zhang, Q. Shi and K.S. Kim, Robust System Design with Built-In Soft Error Resilience, IEEE Computer, Vol. 38, No. 2, pp.43-52, Feb. (2005).

DOI: 10.1109/mc.2005.70

Google Scholar

[10] Gardiner KT, Yakovlev A and Bystrov A., A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits, International On-Line Testing Symposium Proceedings, Heraklion, Crete, Greece: IEEE Computer Society.

DOI: 10.1109/iolts.2007.5

Google Scholar