Lock-Time Behavior of Charge Pump PLLs Employing Oscillators with Non-Linear Frequency Tuning Characteristics

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In this paper we investigate the lock time behavior of charge pump phase locked loops (CP-PLLs) which employ voltage controlled oscillators (VCOs) with non-linear frequency tuning characteristics. Since non-linear tuning characteristics leads to variable tuning gain (Kvco), we extend the state space analysis of PLLs to account for tuning gain variations. The frequency behavior is approximated by a polynomial which fits the equally spaced data points of tuning curve best in a least-square sense. We have analytically evaluated the integrals arising from high order terms in polynomial representation and migrated to state space analysis. The method is validated by simulating the lock-time process of a VCO with varying tuning gain and comparing the results with commercial PLL simulation software.

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52-59

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August 2016

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© 2016 Trans Tech Publications Ltd. All Rights Reserved

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[1] S. Cicero, Architectures for RF Frequency Synthesizers, Kluwer Acad. Pub., New York, US, (2003).

Google Scholar

[2] Electromagnetic compatibility and radio spectrum matters (ERM); Land mobile service; Radio equipment intended for the transmission of data using constant or non-constant envelope modulation and having an antenna connector. ETSI EN 300 113-2 V1. 5. 1 (2011-05).

Google Scholar

[3] Land mobile FM or PM communications equipment measurement and performance standards TIA-603-C (2004-08).

Google Scholar

[4] M. Hinz, I. Konenkamp, E. Horneber Behavioral Modeling and simulation of PLLs for RF front end, IEEE Midwest Symposium on Circuits and Systems, Lansing, MI, pp.194-197, Aug. (2000).

DOI: 10.1109/mwscas.2000.951618

Google Scholar

[5] R. E. Best, Phase locked Loops, 4th ed., McGraw-Hill, Switzerland, (1995).

Google Scholar

[6] M. Perrot, M. D. Trott, C. G. Sodini, A Modeling Approach for Σ-Δ Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis., IEEE Jour. of Solid. State Circuits, vol. 37, no 8, pp.1028-1038, Aug. (2002).

DOI: 10.1109/jssc.2002.800925

Google Scholar

[7] M. Perrot, Fast and Accurate Behavioral simulation of Fractional-N Frequency Synthesizers and Other PLL/DLL Circuits, in Proc. Design Automation Conf., June 2002, pp.498-503.

DOI: 10.1109/dac.2002.1012676

Google Scholar

[8] V. S. Sadeghi, H. M. Naimi, M. P. Kennedy The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better" , IEEE Tran. On Circ. Syst. -2: Express Briefs , vol. 60, no 12, pp.862-866 Dec. (2013).

DOI: 10.1109/tcsii.2013.2285968

Google Scholar

[9] V. R. Gonzalez-Diaz, A. Pena-Perez, F. Maloberti Fractional Frequency Synthesizers with Low Order Time-Variant Digital Sigma-Delta Modulator, IEEE Tran. On Circ. Syst. -2: Regular Papers , vol. 59, no 5, pp.969-978 May (2012).

DOI: 10.1109/tcsi.2012.2191317

Google Scholar

[10] F. Gardner, Charge Pump Phase-Lock Loops , IEEE Trans. Commun, vol. COM-28, pp.1849-1858, Nov. (1980).

DOI: 10.1109/tcom.1980.1094619

Google Scholar

[11] P.K. Hanumolu, M. Brownlee, K. Mayaram, U. Moon, Analysis of Charge-Pump Phase Locked Loops, IEEE Tran. On Circ. Syst., vol. 51, no 9, pp.1665-1674 Sept. (2004).

DOI: 10.1109/tcsi.2004.834516

Google Scholar

[12] M. Guermandi, E. Franchi, A. Gnudi, On the Simulation of Fast Settling Charge Pump PLLs up to Fourth Order, Int. J. Circ. Theor. Appl., vol. 39, pp.1257-1273, Jun. (2011).

DOI: 10.1002/cta.700

Google Scholar

[13] H. B. Dwigth, Table of integrals and other mathematical data, MacMillan, New York, (1961).

Google Scholar