A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

Yue Hu; Hao Wang; De Wen Wang; Cai Xia Du; Miao Miao Ma; Jin Yang; Jin He

doi:10.4028/www.scientific.net/AMR.1096.514

Paper Titles

Electrochromic Porperties of Fluorescent Dye Doped Poly(3,4-ethylenedioxythiophene) with Different Polymerization Times
p.492

A Novel PNIN Barrier Controlled Tunnel FET
p.497

The New Study Based on a Dual Ion Implantation PSD Structure
p.503

Mesoporous Ce_xZr_1-_xO₂ Mixed Oxides Supported Cr-V-O Nanocatalysts for Dehydrogenation of Propane to Propene
p.509

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region
p.514

Molecular Dynamic Study on Thermal Conductivity of Methyl-Chemisorption Carbon Nanotubes
p.520

Reduction Kinetics of Nano-Sized Nickel Ferrite for the Production of Metallic Alloys
p.524

Application of Phase Change Materials in Buildings
p.533

Experimental Study of Factors on the Conductive Properties of Carbon Fiber Reinforced Concrete
p.538

HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 1096A 600V-Class Partial SOI LDMOS with Step-Doped...

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

Abstract:

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Advanced Materials Research (Volume 1096)

Pages:

514-519

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.1096.514

Citation:

Cite this paper

Online since:

April 2015

Authors:

Yue Hu*, Hao Wang, De Wen Wang, Cai Xia Du, Miao Miao Ma, Jin Yang, Jin He

Keywords:

Breakdown Voltage (BV), Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS), On-Resistance, Partial Silicon-On-Insulator (PSOI)

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] S. Kim, J. G. Fossum, and R. K. Williams, New physical insights and models for high-voltage LDMOST IC CAD, IEEE Trans. Electron Devices, vol. 38, no. 7, p.1641–1649, Jul. (1991).

DOI: 10.1109/16.85161

Google Scholar

[2] J. C. Mitros, C. -Y. Tsai, H. Shichijo, M. Kunz, A. Morton, D. Goodpaster, D. Mosher, and T. R. Efland, High-voltage drain extended MOS transistors for 0. 18-μm logic CMOS process, IEEE Trans. Electron Devices, vol. 48, no. 48, p.1751–1755, Jul. (2001).

DOI: 10.1109/16.936703

Google Scholar

[3] A. S. Kashyap, H. A. Mantooth, T. A. Vo, and M. Mojarradi, Compact modeling of LDMOS transistors for extreme environment analog circuit design, IEEE Trans. Electron Devices, vol. 57, no. 6, p.1431–1439, Jun. (2010).

DOI: 10.1109/ted.2010.2046073

Google Scholar

[4] C. -T. Wang and M. -D. Ker, ESD protection design with lateral DMOS transistor in 40-V BCD technology, IEEE Trans. Electron Devices, vol. 57, no. 12, p.3395–3404, Dec. (2010).

DOI: 10.1109/ted.2010.2079530

Google Scholar

[5] E. Arnold, Silicon-on-insulator devices for high voltage and power IC applications, J. Electrochem. Soc., vol. 141, no. 77, p.1983–1988, Jul. (1994).

DOI: 10.1149/1.2055040

Google Scholar

[6] X. R. Luo, Y. Wang, H. Deng, J. Fan, T. Lei, and Y. Liu, Novel low-k dielectric buried-layer high-voltage LDMOS on partial SOI, IEEE Trans. Electron Devices, vol. 57, no. 2, p.535–538, Feb. (2010).

DOI: 10.1109/ted.2009.2037372

Google Scholar

[7] X. R. Luo, B. Zhang, and Z. J. Li, New high-voltage (> 1200 V) MOSFET with the charge trenches on partial SOI, IEEE Trans. Electron Devices, vol. 55, no. 7, p.1756–1761, Jul. (2008).

DOI: 10.1109/ted.2008.924048

Google Scholar

[8] B. X. Duan, B. Zhang, and Z. J. Li, A new partial SOI power device structure with P-type buried layer, Solid State Electron., vol. 49, no. 12, p.1965–1968, Dec. (2005).

DOI: 10.1016/j.sse.2005.09.012

Google Scholar

[9] F. Udrea, A. Popescu, and W. Milne, Breakdown analysis in JI, SOI and partial SOI power structures, in Proc. IEEE Int. SOI Conf., Oct. 1997, p.102–103.

DOI: 10.1109/soi.1997.634953

Google Scholar

[10] J.M. Park, T. Grasser, H. Kosina, and S. Selberherr, A numerical study of partial-SOI LDMOSTFET power devices, Solid State Electron., vol. 47, no. 2, p.275–281, Feb. (2003).

DOI: 10.1016/s0038-1101(02)00207-1

Google Scholar

[11] H. Funaki, Y. Yamaguchi, K. Hirayama, and A. Nakagawa, New 1200 V MOSFET structure on SOI with SIPOS shielding layer, in Proc. ISPSD, Jun. 1998, p.25–28.

DOI: 10.1109/ispsd.1998.702621

Google Scholar

[12] A. Nakagawa, N. Yasuhara, and Y. Baba, Breakdown voltage enhancement for devices on thin silicon layer or silicon dioxide film, IEEE Trans. Electron Devices, vol. 38, no. 7, p.1650–1654, Jul. (1991).

DOI: 10.1109/16.85162

Google Scholar

[13] X. R. Luo, B. Zhang, Z. J. Li, Y. F. Guo, X. Tang, and Y. Liu, A novel 700-V SOI LDMOS with double-sided trench, IEEE Electron Device Lett., vol. 28, no. 5, p.422–424, May (2007).

DOI: 10.1109/led.2007.894648

Google Scholar

[14] X. R. Luo, Z. J. Li, B. Zhang, D. P. Fu, Z. Zhan, K. F. Chen, S. D. Hu, Z. Zhang, C. Feng, and B. Yan, Realization of high voltage (> 700 V) in new SOI devices with a compound buried layer, IEEE Electron Device Lett., vol. 29, no. 12, p.1395–1397, Nov. (2008).

DOI: 10.1109/led.2008.2007307

Google Scholar