Paper Titles

Compact Model Analysis for Low Voltage OFETs with Electrolytic Gate Dielectrics: Toward a Universal Model for Poly(3-Hexylthiophene) P3HT OFETs
p.3

Zinc Sulphide Quantum Dots’ Applications in Antibacterial as well as Estimation of E.Coli Concentration by Fabricating Mem-Mode Devices
p.11

Principles of Logic Design with Nanoscale Thin Film Memristive Systems for High Performance Digital Circuit Applications
p.19

Effect of Quantum Dots Dispersion on the Structural, Optical, and Thermal Properties of Liquid Crystal System
p.33

Effect of Atmospheric Dielectric Barrier Discharge on Optical, Electrical and Surface Properties of ZnO Film
p.43

Light Induced Synthesis of Ag Nanorods for Potential Application as Optical Filter Tailored to Visible Domain
p.53

Transition from Reflective to Energy-Storing Self-Illumination in Road Markings: A Review
p.63

Structural, Thermal, and Magnetic Characterization Analysis of Synthesized Fe₃O₄-Spinel Ferrite Nanoparticles
p.79

HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 1176Principles of Logic Design with Nanoscale Thin...

Principles of Logic Design with Nanoscale Thin Film Memristive Systems for High Performance Digital Circuit Applications

Article Preview

Abstract:

The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

You might also be interested in these eBooks

Modern Materials for Engineering and Research

Functional and Special Materials

Info:

Periodical:

Advanced Materials Research (Volume 1176)

Pages:

19-31

DOI:

https://doi.org/10.4028/p-90x9b8

Citation:

Cite this paper

Online since:

April 2023

Authors:

Mayank Chakraverty*, V.N. Ramakrishnan

Keywords:

AND, CMOS, Gate, IMPLY, Logic, MAGIC, Memristors, MRL, NAND, NOR, OR

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

© 2023 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] Chua LO, "Memristor—The Missing Circuit Element", IEEE Trans Circuit Theory, Vol. 18, issue 5, pp.507-519, Sept. 1971.

DOI: 10.1109/tct.1971.1083337

[2] Chua LO, Kang SM, "Memristive Devices and Systems", Proc IEEE Vol. 64, issue 2, p.209–223, Feb. 1976.

[3] Strukov DB, Snider GS, Stewart DR, Williams RS, "The missing memristor found", Nature 453: 80–83, May 2008.

DOI: 10.1038/nature06932

[4] R. S. Williams, "How We Found the Missing Memristor," IEEE Spectrum, Vol. 45, no. 12, pp.28-35, Dec. 2008.

DOI: 10.1109/mspec.2008.4687366

[5] M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R. Stewart, et al., "Switching dynamics in titanium dioxide memristive devices", Journal of Applied Physics, vol. 106, no. 7, p.074508, 2009.

DOI: 10.1063/1.3236506

[6] Chua, L, "Resistance switching memories are memristors", Appl. Phys. A, Vol. 102, p.765–783, Jan. 2011.

DOI: 10.1007/s00339-011-6264-9

[7] Y. N. Joglekar and S. J. Wolf, "The elusive memristor: Properties of basic electrical circuits", European Journal of Physics, vol. 30, no. 4, pp.661-675, 2009.

DOI: 10.1088/0143-0807/30/4/001

[8] Chris Yakopcic, Tarek M. Taha, Guru Subramanyam and Robinson E. Pino, "Generalized Memristive Device SPICE Model and its Application in Circuit Design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE), vol. 32, no. 8, pp.1201-1214, August 2013.

DOI: 10.1109/tcad.2013.2252057

[9] Joel Molina-Reyes, Luis Hernandez-Martinez, "Understanding the Resistive Switching Phenomena of Stacked Al/Al2O3/Al Thin Films from the Dynamics of Conductive Filaments", Complexity, vol. 2017, 2017.

DOI: 10.1155/2017/8263904

[10] Sanghyeon Choi, Seonggil Ham and Gunuk Wang, "Memristor Synapses for Neuromorphic Computing, Memristors - Circuits and Applications of Memristor Devices", Alex James, IntechOpen, DOI: 10.5772/intechopen.85301, March 2019.

DOI: 10.5772/intechopen.85301

[11] Burr GW, Shelby RM, Sebastian A, et al, "Neuromorphic computing using non-volatile memory", Adv Phys X, Vol. 2, issue 1, p.89–124, 2017.

[12] M. Hu et al., "Memristor crossbar-based neuromorphic computing system: A case study", IEEE transactions on neural networks and learning systems, Vol. 25, pp.1864-1878, 2014.

DOI: 10.1109/tnnls.2013.2296777

[13] Y. Zhao et al., "A compact model for drift and diffusion memristor applied in neuron circuits design", IEEE Trans. Electron Devices, Vol. 65, no. 10, pp.4290-4296, Oct. 2018.

DOI: 10.1109/ted.2018.2865225

[14] Sung Hyun Jo, Ting Chang, Idongesit Ebong, Bhavitavya B. Bhadviya, Pinaki Mazumder, and Wei Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems", Nano Letters, Vol. 10, no. 4, pp.1297-1301, (2010)

DOI: 10.1021/nl904092h

[15] S. Kvatinsky, E. G. Friedman, A. Kolodny and U. C. Weiser, "TEAM: Threshold adaptive memristor model", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 60, no. 1, pp.211-221, Jan. 2013.

DOI: 10.1109/tcsi.2012.2215714

[16] S. Kvatinsky, M. Ramadan, E. G. Friedman and A. Kolodny, "VTEAM: A general model for voltage-controlled memristors", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 62, no. 8, pp.786-790, Aug. 2015.

DOI: 10.1109/tcsii.2015.2433536

[17] Z. Jiang et al., "A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification," in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp.1884-1892, May 2016.

DOI: 10.1109/ted.2016.2545412

[18] D. Biolek, Z. Kolka, V. Biolkova and Z. Biolek, "Memristor models for SPICE simulation of extremely large memristive networks", Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp.389-392, May 2016.

DOI: 10.1109/iscas.2016.7527252

[19] Biolek D, Biolek Z, Biolková V., "Interpreting area of pinched memristor hysteresis loop", Electron Lett, Vol. 50, no. 2, p.74–75, 2014.

DOI: 10.1049/el.2013.3108

[20] Biolek D., Biolek Z., Biolková V., "Pinched hysteretic loops of ideal memristors, memcapacitors and meminductors must be 'selfcrossing'", Electron. Lett., Vol. 47, no. 25, p.1385 – 1387, 2011.

DOI: 10.1049/el.2011.2913

[21] Chakraverty M, Ramakrishnan VN, "A Qualitative Study of Materials and Fabrication Methodologies for Two Terminal Memristive Systems" Materials Today: Proceedings. Elsevier Ltd, p.1628–1637, 2019.

DOI: 10.1016/j.matpr.2020.02.160

[22] F. Gul, "Circuit Implementation of Nano-Scale TiO2 Memristor Using Only Metal-Oxide-Semiconductor Transistors," in IEEE Electron Device Letters, vol. 40, no. 4, pp.643-646, April 2019.

DOI: 10.1109/led.2019.2899889

[23] R. Berdan, C. Lim, A. Khiat, C. Papavassiliou and T. Prodromakis, "A Memristor SPICE Model Accounting for Volatile Characteristics of Practical ReRAM," in IEEE Electron Device Letters, vol. 35, no. 1, pp.135-137, Jan. 2014.

DOI: 10.1109/led.2013.2291158

[24] T. Prodromakis, B. P. Peh, C. Papavassiliou and C. Toumazou, "A Versatile Memristor Model with Nonlinear Dopant Kinetics," in IEEE Transactions on Electron Devices, vol. 58, no. 9, pp.3099-3105, Sept. 2011.

DOI: 10.1109/ted.2011.2158004

[25] Chris Yakopcic, Tarek M. Taha, Guru Subramanyam, Robinson E. Pino and Stanley Rogers, "A Memristor Device Model", IEEE Electron Device Letters, Vol. 32, no. 10, pp.1436-1438, October 2011.

DOI: 10.1109/led.2011.2163292

[26] Jinxiang Zha, He Huang, Tingwen Huang, Jinde Cao, Ahmed Alsaedi and Fuad E. Alsaadi, "A General Memristor Model and its applications in programmable analog circuits", Neurocomputing, vol. 267, pp.134-140, 2017.

DOI: 10.1016/j.neucom.2017.04.057

[27] J. J. Yang, M. D. Pickett, X. Li, D. R. Stewart, and R. S. Williams, "Memristive switching mechanism for metal/oxide/metal nanodevice", Nature Nanotechnology, page 429-433, 2008.

DOI: 10.1038/nnano.2008.160

[28] R. S. Williams, and D. B. Strukov, "Exponential ionic drift: Fast switching and low volatility of thin- film memristor", Applied Physics A. Material Sci. Process, page 515-519, 2009.

DOI: 10.1007/s00339-008-4975-3

[29] Mayank Chakraverty, VN Ramakrishnan, "Temperature Dependent Carrier Transport in Hydrogenated Amorphous Semiconductors for Thin Film Memristive Applications", Materials Science Forum, Vol. 1048, pp.182-188, Trans Tech Publications, Switzerland, Jan 2022, ISSN: 1662-9752.

DOI: 10.4028/www.scientific.net/msf.1048.182

[30] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart and R. S. Williams, "Memristive Switches Enable 'Stateful' Logic Operations via Material Implication", Nature, vol. 464, pp.873-876, April 2010.

DOI: 10.1038/nature08940

[31] E. Lehtonen, J. H. Poikonen and M. Laiho, "Two Memristors Suffice to Compute All Boolean Functions", Electronics Letters, vol. 46, no. 3, pp.239-240, February 2010.

DOI: 10.1049/el.2010.3407

[32] Y. V. Pershin and M. Di Ventra, "Practical Approach to Programmable Analog Circuits with Memristors", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 8, pp.1857-1864, August 2010.

DOI: 10.1109/tcsi.2009.2038539

[33] D. B. Strukov and K. K. Likharev, "CMOL FPGA: a Reconfigurable Architecture for Hybrid Digital Circuits with Two- Terminal Nanodevices", Nanotechnology, vol. 16, no. 6, pp.888-900, June 2005.

DOI: 10.1088/0957-4484/16/6/045

[34] G. S. Rose and M. R. Stan, "A Programmable Majority Logic Array Using Molecular Scale Electronics", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 11, pp.2380-2390, November 2007.

DOI: 10.1109/tcsi.2007.907860

[35] Y. V. Pershin and M. Di Ventra, "Neuromorphic digital and quantum computation with memory circuit elements", Proc. IEEE, vol. 100, no. 6, pp.2071-2080, Jun. 2012.

DOI: 10.1109/jproc.2011.2166369

[36] S. Shin, K. Kim and S.-M. Kang, "Reconfigurable stateful NOR gate for large-scale logic-array integrations", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 58, no. 7, pp.442-446, Jul. 2011.

DOI: 10.1109/tcsii.2011.2158253

[37] J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart and R. S. Williams, "Memristive switching mechanism for metal/oxide/metal nanodevices", Nature Nanotechnol., vol. 3, pp.429-433, Jul. 2008.

DOI: 10.1038/nnano.2008.160

[38] S. Kvatinsky, E. G. Friedman, A. Kolodny and U. C. Weiser, "Memristor-based material implication (IMPLY) logic: Design principles and methodologies", IEEE Trans. Very Large Scale Integr. (VLSI), vol. 22, no. 10, pp.2054-2066, Oct. 2013.

DOI: 10.1109/tvlsi.2013.2282132

[39] E. Lehtonen and M. Laiho, "Stateful implication logic with memristors", Proc. IEEE/ACM Int. Symp. Nanosc. Archit., pp.33-36, Jul. 2009.

DOI: 10.1109/nanoarch.2009.5226356

[40] E. Linn, R. Rosezin, C. Kügeler and R. Waser, "Complementary resistive switches for passive nanocrossbar memories", Nature Mater., vol. 9, no. 5, pp.403-406, Apr. 2010.

DOI: 10.1038/nmat2748

[41] S. Kvatinsky et al., "MAGIC—Memristor-Aided Logic", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 11, pp.895-899, Nov. 2014.

DOI: 10.1109/tcsii.2014.2357292

[42] N. Talati, S. Gupta, P. Mane and S. Kvatinsky, "Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)", IEEE Transactions on Nanotechnology, vol. 15, no. 4, pp.635-650, July 2016.

DOI: 10.1109/tnano.2016.2570248

[43] S. Kvatinsky et al., "MRL—Memristor ratioed logic", Proc. Int. Cellular Nanoscale Netw. Appl., pp.1-6.

[44] J. J. Yang, D. B. Strukov and D. R. Stewart, "Memristive devices for computing", Nat. Nanotechnol., vol. 8, pp.13-24, Jan. 2013.

[45] L. Qu, X. Cui, X. Xu, X. Cui and Y. Ma, "The Multi-input MRL Logic Gate and Its Application", IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp.1-2, June. 2019.

DOI: 10.1109/edssc.2019.8753985