I2C-Bus Design Based on FPGA

Abstract:

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Introduced field programmable gate array FPGA with I2C bus interface device interface design. Programming with VHDL, using general FPGA I/O port to generate I2C bus interface signal timing, achieved FPGA with I2C-bus devices data communication, went through the simulation test, given the application example of FPGA with I2C-bus EEPROOM chip AT24C02 connected hardware design.

Info:

Periodical:

Advanced Materials Research (Volumes 179-180)

Edited by:

Garry Zhu

Pages:

528-533

DOI:

10.4028/www.scientific.net/AMR.179-180.528

Citation:

D. Cao et al., "I2C-Bus Design Based on FPGA", Advanced Materials Research, Vols. 179-180, pp. 528-533, 2011

Online since:

January 2011

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Price:

$35.00

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