A New Clock Synchronization Method for Multi-FPGA Systems
A novel clock synchronization scheme is proposed in this paper, which smartly takes the advantages of the inner delay-locked loop(DLL) to compensate for the delay generated by board-level feedback, combining with conventional external clock tree scheme to achieve the system clock synchronization.
Helen Zhang, Gang Shen and David Jin
C. C. Zhang et al., "A New Clock Synchronization Method for Multi-FPGA Systems", Advanced Materials Research, Vols. 204-210, pp. 907-910, 2011