A New Clock Synchronization Method for Multi-FPGA Systems

Cheng Chang Zhang; Li Sheng Yang; Xiao Ping Hu; Hong Yang; Ping Li

doi:10.4028/www.scientific.net/AMR.204-210.907

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 204-210A New Clock Synchronization Method for Multi-FPGA...

A New Clock Synchronization Method for Multi-FPGA Systems

Abstract:

A novel clock synchronization scheme is proposed in this paper, which smartly takes the advantages of the inner delay-locked loop(DLL) to compensate for the delay generated by board-level feedback, combining with conventional external clock tree scheme to achieve the system clock synchronization.

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Periodical:

Advanced Materials Research (Volumes 204-210)

Pages:

907-910

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.204-210.907

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Online since:

February 2011

Authors:

Cheng Chang Zhang, Li Sheng Yang, Xiao Ping Hu, Hong Yang, Ping Li

Keywords:

Clock, Multi-FPGA System, Synchronisation

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References

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