Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors

Abstract:

Article Preview

The feature of implementing of loops with self-compensation of CMOS transistors differential resistance in the gain stages is reviewed. Shown that these compensation loops reduce the parametric sensitivity of the stage and the transistors output capacitance influence on a range of operating frequencies. А set of loops of cancellation of the CMOS transistors parasitic parameters influence on stage cutoff frequency was proposed. The conclusions were made. An example of cost-stage high gain was given.

Info:

Periodical:

Edited by:

Jun Hu and Qi Luo

Pages:

589-596

DOI:

10.4028/www.scientific.net/AMR.320.589

Citation:

S. Krutchinsky et al., "Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors", Advanced Materials Research, Vol. 320, pp. 589-596, 2011

Online since:

August 2011

Export:

Price:

$35.00

In order to see related information, you need to Login.

In order to see related information, you need to Login.