Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors

Sergey Krutchinsky; Vasiliy Bespyatov; Alexander Korolev; Eugeniy Zhebrun; Anton Zolotarev

doi:10.4028/www.scientific.net/AMR.320.589

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 320Circuitry Design Feature of Stages with High-Gain...

Circuitry Design Feature of Stages with High-Gain Coefficient on Field-Effect Transistors

Abstract:

The feature of implementing of loops with self-compensation of CMOS transistors differential resistance in the gain stages is reviewed. Shown that these compensation loops reduce the parametric sensitivity of the stage and the transistors output capacitance influence on a range of operating frequencies. А set of loops of cancellation of the CMOS transistors parasitic parameters influence on stage cutoff frequency was proposed. The conclusions were made. An example of cost-stage high gain was given.

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Periodical:

Advanced Materials Research (Volume 320)

Pages:

589-596

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.320.589

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Online since:

August 2011

Authors:

Sergey Krutchinsky, Vasiliy Bespyatov, Alexander Korolev, Eugeniy Zhebrun, Anton Zolotarev

Keywords:

Component, Differential Stage, Integral Project Blocks, Microcircuitry, Structural Synthesis

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References

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