The Design and Implementation of a Parallel Configurable Paseudorandom Sequence Generator

Jun Yang; Ga Zhao; Xiao Jun Wang; Ping Ping Shu; Heng Fen Yang

doi:10.4028/www.scientific.net/AMR.468-471.1903

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 468-471The Design and Implementation of a Parallel...

The Design and Implementation of a Parallel Configurable Paseudorandom Sequence Generator

Abstract:

In this paper, we study the implements a data rate can be adjusted, m series can be equipped with pseudo-random series of sequence generator. This design in the basis of linear feedback shift register, through the linear feedback function to produce mould the longest m sequence. In order to carry on it, we use the hardware description language VHDL, take advantage of the FPGA reconfigurability and flexibility, using Quartus II 8.0 for the integrated wiring, and give the Model simulation waveforms. For the sake of verifying the feasibility of this design, we adapt it to the DE2 board, and with an oscilloscope and other equipment were tested.

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Periodical:

Advanced Materials Research (Volumes 468-471)

Pages:

1903-1906

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.468-471.1903

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Online since:

February 2012

Authors:

Jun Yang, Ga Zhao, Xiao Jun Wang, Ping Ping Shu, Heng Fen Yang

Keywords:

Field-Programmable Gate Array (FPGA), Linear Feedback Shift Registers, M-Sequence, Pseudo-Random

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References

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