Paper Titles
Research of Force in Piercing Process by FEM Simulation
p.62
Non-Oscillatory Solutions of Linear Delay Functional Differential System of Neutral Type
p.66
Quantitative Analysis of the Strategic Decision on Graduate Employment
p.70
Study on Differential GPS (DGPS): Method for Reducing the Measurement Error of CNNS
p.75
An Optimization Design in the HV nLDMOS by Taguchi Method
p.81
Teaching and Research on Assembly Language
p.85
Liquid-Liquid Two-Phase Flow Patterns and Mass Transfer Characteristics in a Circular Microchannel
p.89
An Improved Hybrid Genetic Algorithm and Performance Study
p.95
An Echo State Network Based on Error Compensation for Prediction of Nonlinear Time Series in Industry
p.99

An Optimization Design in the HV nLDMOS by Taguchi Method

Article Preview

Abstract:

This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L8(27). By this way, it can decrease the times of experiment much effectively.

You might also be interested in these eBooks
Advanced Composite Materials View Preview

Info:

Periodical:

Advanced Materials Research (Volumes 482-484)

Pages:

81-84

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.482-484.81

Citation:

Cite this paper

Online since:

February 2012

Authors:

Shen Li Chen, Tzung Shian Wu, Yun Ru Chen, Hung Wei Chen, Chun Hsing Shih, H.H. Chen

Keywords:

Adaptive Layer, Buried Layer, Holding Voltage (Vh), HV (High-Voltage) Device, Latch-up Effect, nLDMOS, Optimization Simulation, Taguchi Method, Trigger Voltage (Vt1)

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

© 2012 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

References

[1] Shen-Li Chen, Tzung-Shian Wu , Hung-Wei Chen, Chun-Hsing Shih, and Po-Ying Chen: IEEE International Conference on Solid-State and Integrated-Circuit Technology (2010), p.1689.

Google Scholar

[2] P. L. Hower, J. Lin, and Steve Merchant: IEEE IEDM (1999), p.8.3.1.

Google Scholar

[3] Madhav S. Phadke: Quality Engineering Using Robust Design (Prentice Hall, US, 1999)

Google Scholar

[4] Ming-Dou Ker, Kun-Hsien Lin: IEEE Electron Device Letters, Vol. 25, No. 9 (2004), p.640.

Google Scholar

[5] M. Heera, V. Dubeca, S. Bychikhina, D. Poganya, E. Gornika, M. Frankb, A. Konradb, J. Schulzc: Microelectronics Reliability , Vol.46 (2006), p.1591.

Google Scholar

[6] Jian-Hsing Lee, Hung-Der Su, Chien-Ling Chan, DH Yang, Jone F. Chen, and KM Wu: International Symposium on Power Semiconductor Devices & ICs (2010), p.303.

Google Scholar