Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Manisha Pattanaik; Balwinder Raj; Shashikant Sharma; Anjan Kumar

doi:10.4028/www.scientific.net/AMR.548.885

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 548Diode Based Trimode Multi-Threshold CMOS Technique...

Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Abstract:

In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit with BPTM 90nm technology at room temperature with supply voltage of 1 V. Diode based trimode Multi-Threshold CMOS technique reduces ground bounce noise by 89.36% and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.

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Periodical:

Advanced Materials Research (Volume 548)

Pages:

885-889

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.548.885

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Online since:

July 2012

Authors:

Manisha Pattanaik, Balwinder Raj, Shashikant Sharma, Anjan Kumar

Keywords:

Ground Bounce Noise, Leakage Current, MTCMOS, Sleep to Active Mode Transition

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References

[1] S.G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, New York: Springer-verlag, (2006).

Google Scholar

[2] Piguet, C. Low Power Electronics Design, CRC Press, (2005).

Google Scholar

[3] V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design , New York: Wiley, (2006).

DOI: 10.1002/0470033371

Google Scholar

[4] R. Bhanuprakash, Manisha Pattnaik, S.S. Rajput and Kaushik Majumdar, Reduction of Leakage Current and Ground Bounce Noise Using High Performance Stacking Power Gating Logic Circuits, Proceedings of IEEE TENCON Singapore, pp.1-6, (2009).

DOI: 10.1109/tencon.2009.5395850

Google Scholar

[5] H. Jiao and V. Kursun, Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits, Proceedings IEEE Asia Symposium on Quality Electron Design, p.64–70, (2009).

DOI: 10.1109/asqed.2009.5206297

Google Scholar

[6] H. Jiao and V. Kursun, Ground-Bounce-Noise Aware Combinational MTCMOS Circuits, IEEE Transactions on Circuits and Systems-1: Regular Papers, Vol. 57, No. 8, pp.2053-2065, (2010).

DOI: 10.1109/tcsi.2010.2041505

Google Scholar