Design of a SoC With High-Speed DDC for Software Radio Receiver

Abstract:

This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

• Periodical: Advanced Materials Research (Volumes 605-607)
• Pages: 1875-1879
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.605-607.1875
• Online since: December 2012
• Authors: Jun Deng, Lin Tao Liu, Yu Jing Li, Xiao Zong Huang, Xu Huang, Lun Cai Liu
• Keywords: High-Speed DDC, OR1200 CPU, SoC, Software Radio Receiver

References

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