Design of the Approved Low Power Energy Recovery Logic Circuit

Jian Ying Shi; Hui Ya Li; Yan Bin Xu

doi:10.4028/www.scientific.net/AMR.662.851

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 662Design of the Approved Low Power Energy Recovery...

Design of the Approved Low Power Energy Recovery Logic Circuit

Abstract:

An approved energy recovery logic circuit (AERL) was designed in this paper. In order to further reduce the power consumption of energy recovery logic circuits, the NMOS transmission gate and NMOS bootstrap technique ware used. The characteristics of the AERL circuit ware simulated using 0.5 micrometer BSIM3V3 spice models in HSPICE. The results show that the AERL circuit has much lower power consumption compared with PT-BCRL, BERL, ECRL and 2N2N-2P logic.

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Periodical:

Advanced Materials Research (Volume 662)

Pages:

851-855

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.662.851

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Online since:

February 2013

Authors:

Jian Ying Shi, Hui Ya Li, Yan Bin Xu

Keywords:

AERL, Energy Recovery Jogic Circuit, Low Power

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