The Analysis of the Process-Induced Channel Stress in N-MOSFET

Abstract:

This research analyzes internal stress in the N-MOSFET. The research has two parts. First, we explore the effect of N-MOSFET channel stress when CESL layer is not utilized. The dimensional effect of spacer upon channel stress in N-MOSFET with variant width of ONO (oxide, nitride, oxide) is compared. Second, with stress applied to CESL and the spacer stressor, long/short channel effects are analyzed. It is demonstrated that when the thickness of CESL and the height of gate increase, the channel stress under the gate dielectric layer becomes tensile, and the performance is improved in the short channel, resulting in the improved performance in the whole N-MOSFET. Therefore, better device characteristics can be expected through the approach disclosed in this paper.

• Periodical: Advanced Materials Research (Volume 699)
• Pages: 440-444
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.699.440
• Online since: May 2013
• Authors: M.J. Twu, R.H. Deng, Z.H. Chen, M.C. Tsai, K.C. Lin, C.H. Liu
• Keywords: Channel Stress, Contact Etch Stop Layer (CESL), n-MOSFET, Spacer Stressor

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