Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

Abstract:

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small R_on resistance, low trigger voltage (V_t1) and high holding voltage (V_h) characteristics. Here, we introduce a deep N⁺-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

• Periodical: Advanced Materials Research (Volumes 732-733)
• Pages: 1207-1211
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.732-733.1207
• Online since: August 2013
• Authors: Shen Li Chen, Tzung Shian Wu
• Keywords: Breakdown Voltage (V_bk), Electrostatic Discharge (ESD), Holding Voltage (V_h), Latch-Up (LU), N⁺ Burried Layer (NBL), N⁺-Type Buried Layer (NBL), nLDMOS, R_on Resistance, Trigger Voltage (V_t1)

References

[1] Ming-Hau Chan, Yu-Tzung Lin, Ying-Yu Tzou: IEEE 6th International Power Electronics and Motion Control Conference (2009), p.1708.

DOI: 10.1109/ipemc.2009.5157668

[2] A. Parayandeh, B. Mahdavikkhah, S.M. Ahsanuzzaman, A. Radic, A. Prodic: IEEE Conference on Energy Conversion Congress and Exposition (2011), p.1229.

DOI: 10.1109/ecce.2011.6063917

[3] Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang: IEEE Electron Device Letters, Vol. 29, Issue 7 (2008), p.762.

[4] Yong Seo Koo, Hyun Duck Lee, Jong Il Won, Yil Suk Yang: International Power Electronics Conference (IPEC 2010), p.248.

[5] H. Tsai and M. Ker: IEEE Trans. on Device and Materials Reliability, Vol. 12, Issue 4 (2012), p.1.

[6] Tuo-Hsin Chien, K.Y. -J. Hsu: IEEE International Reliability Physics Symposium (2008), p.629.

[7] V.A. Vashchenko, D.J. LaFonteese: IEEE 31st EOS/ESD Symposium (2009), p.1.

[8] Shen-Li Chen, Min-Hua Lee, Tzung-Shian Wu, Yi-Sheng Lai, Chun-Ju Lin, Hsun-Hsiang Chen: International Conference on Intelligent Technologies and Engineering Systems (2012), p. P2-7-1.

[9] Shen-Li Chen, Tzung-Shian Wu, Yun-Ru Chen, Hung-Wei Chen, Chun-Hsing Shih, and H.H. Chen: Journal of Advanced Materials Research, Vols. 482-484 (2012), p.81.

[10] Jian-Hsing Lee, S.H. Chen, Y.T. Tsai, D.B. Lee, F.H. Chen, W.C. Liu, C.M. Chung, S.L. Hsu, J.R. Shih, A.Y. Liang, K. Wu: 19th International Symposium on Power Semiconductor Devices and IC's (2007), p.173.

DOI: 10.1109/ispsd.2007.4294960

[11] T. Imoto, K. Mawatari, K. Wakiyama, T. Kobayashi, M. Yano, M. Shinohara, T. Kinoshita, H. Ansai: IEEE International Reliability Physics Symposium (2009), p.663.

DOI: 10.1109/irps.2009.5173326

[12] J. Perez-Gonzalez, J. Sonsky, A. Heringa, J. Benson, P.Y. Chiang, C.W. Yao, R.Y. Sua: 21st International Symposium on Power Semiconductor Devices & IC's (2009), p.61.

DOI: 10.1109/ispsd.2009.5158001

[13] Yanying Wang, Dong Zhang, Yuqiang Lv, Dawei Gong, Kai Shao, Zhongjian Wang, Dawei He, Xinhong Cheng: International Workshop on Junction Technology (2010), p.1.

[14] S. Shahbazi, M. Fathipour: International Semiconductor Device Research Symposium (2011), p.1.

[15] B.K. Boksteen, S. Dhar, A. Heringa, G.E.J. Koops, R.J.E. Hueting: International Symposium on Power Semiconductor Devices and ICs (2012), p.145.

DOI: 10.1109/ispsd.2012.6229044