DLL-Based Receiver for High Speed Data Transmission

Pu Luo

doi:10.4028/www.scientific.net/AMR.753-755.2471

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 753-755DLL-Based Receiver for High Speed Data...

DLL-Based Receiver for High Speed Data Transmission

Abstract:

For modern high speed DAC, receiving data reliably from FPGA is a big challenge, data-independent skew is the major problem. usually system employ data clock while transmitting LVDS data from FPGA. then LVDS data is latched by delayed data clock which generated by DLL in chip. Because DLL has a negative feedback loop, system suffer small effect of PVT variations, robustness is guaranteed. The receiving circuits were implemented in a all-digital 0.18μm CMOS technology ,occupies 0.7 mm² of area. It operates in the frequency range of 20 MHz~600 MHz.

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Periodical:

Advanced Materials Research (Volumes 753-755)

Pages:

2471-2474

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.753-755.2471

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Online since:

August 2013

Authors:

Pu Luo*

Keywords:

Data Clock, Data-Independent Skew, DLL, Negative Feedback Loop

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