A 1.25Gsps 0.35um SiGe BiCMOS Track and Hold Circuit

Rong Bin Hu; Xiao Ying Zhang

doi:10.4028/www.scientific.net/AMR.753-755.2475

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 753-755A 1.25Gsps 0.35um SiGe BiCMOS Track and Hold...

A 1.25Gsps 0.35um SiGe BiCMOS Track and Hold Circuit

Abstract:

In this paper, a novel track and hold circuit in 0.35um SiGe BiCMOS process is presented. Compared to the traditional one, several improvements are made on the proposed track and hold circuit. At first, multistage architecture is used, which has better isolation. Secondly, a saturation protection circuit is designed into the track and hold circuit to prevent the NPN transistor from getting into saturation state. The simulation results show that the proposed track and hold circuit has a SFDR of 82dB and SNR of 76dB at the sampling rate of 1.25Gsps. Further simulation proved that the proposed track and hold circuit has better performances than the traditional one.

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Periodical:

Advanced Materials Research (Volumes 753-755)

Pages:

2475-2478

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.753-755.2475

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Online since:

August 2013

Authors:

Rong Bin Hu, Xiao Ying Zhang

Keywords:

ADC, Feedback, NPN, Track and Hold Circuit

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References

[1] B. Min , P. Kim , F. W. Bowman III, D. M. Boisvert and A. J. Aude A 69 mW 10-bit 80-MSample/s pipelined CMOS ADC, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.2031-2039 (2003).

DOI: 10.1109/jssc.2003.819166

Google Scholar

[2] J. Arias , V. Boccuzzi , L. Enriquez , D. Bisbal , M. Banu and J. Barbolla Low-power pipeline ADC for wireless LANs, IEEE J. Solid-State Circuits, vol. 39, no. 8, pp.1338-1340 (2004).

DOI: 10.1109/jssc.2004.831477

Google Scholar

[3] D. Kurose , T. Ito , T. Ueno , T. Yamaji and T. Itakura 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers, IEEE J. Solid-State Circuits, vol. 41, no. 7, pp.1589-1595 (2006).

DOI: 10.1109/jssc.2006.873888

Google Scholar

[4] P. Wu , V. Luen and H. Luong A 1 V 100-MS/s 8 bit CMOS switched- opamp pipelined ADC using loading free architecture, IEEE J. Solid-State Circuits, vol. 42, no. 4, pp.730-738 (2007).

DOI: 10.1109/jssc.2007.891666

Google Scholar

[5] J. Li and U. Moon A 1. 8 V 67 mW 10-bit 100 Ms/s pipelined ADC using time shifted CDS technique, IEEE J. Solid-State Circuits, vol. 39, no. 9, pp.1468-1476 (2004).

DOI: 10.1109/jssc.2004.829378

Google Scholar

[6] B. Lee , B. Min , G. Manganarom and J. W. Valvano A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC, IEEE J. Solid- State Circuits, vol. 43, no. 12, pp.2613-2619 (2008).

DOI: 10.1109/jssc.2008.2006309

Google Scholar

[7] S. Park, Y. Palaskas, and M. P. Flynn, A 4 GS/s 4b flash ADC in 0. 18μm CMOS, in IEEE ISSCC Dig., 2006, pp.570-571, 674.

Google Scholar

[8] Nasrollaholhosseini, S.H.; Mashhadi, S.B.; Lotfi, R. Power reduction techniques in a 6 bit 1 GSPS flash ADC, Electrical Engineering (ICEE), 2012 20th Iranian Conference on, On page(s): 228 - 231.

DOI: 10.1109/iraniancee.2012.6292358

Google Scholar