VLSI Implementation of Multi-Transform for H.264 and AVS-M

Abstract:

This paper proposes a new architecture of multiple transforms for H.264/AVC and AVS-M. With the proposed architecture, H.264 4×4 inverse integer transform, H.264 4×4 Hadamard transform and AVS-M 4×4 inverse integer transform can be merged to process. Due to a new fast 1-D transform algorithm adopted by the architecture, multiple transforms can share the common resources to reduce the hardware cost. The data processing rate of the proposed architecture is 8 pixels per cycle. Under the SMIC 0.18um standard cell library, the optimum operating frequency achieves to 200MHz, and the data throughput rate achieves to 1.6G pixels per second with the hardware cost of 5461 gates. The power consumption is 3.0831mW when the global operating voltage is 1.8V. Due to its high throughput , the proposed design achieve the requirement of 3G applications obviously.

• Periodical: Advanced Materials Research (Volumes 765-767)
• Pages: 2724-2727
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.765-767.2724
• Online since: September 2013
• Authors: Miao Song, Xiao Li Chen, Ze Fang Wang
• Keywords: AVS-M, H.264/AVC, Instruct Hadamard Transform, Multiple Transform

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