Model of Video Encryption Based on FPGA

Jin Hui Zhao; Xiao Hong Wang

doi:10.4028/www.scientific.net/AMR.791-793.1497

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 791-793Model of Video Encryption Based on FPGA

Model of Video Encryption Based on FPGA

Abstract:

On the Internet, most of media information is transmitted in plaintext. Some others can easily tamper or intercut the information, so there are threats to those information transmitted in plaintext. This paper designs a model of video encryption which uses AES algorithm and the model is based on FPGA platform. The model does the encryption in paralleling on XUPV5-110T development board. The encryption model can ensure the security and integrity of media information during the transmission process between a certain links on the network.

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Periodical:

Advanced Materials Research (Volumes 791-793)

Pages:

1497-1500

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.791-793.1497

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Online since:

September 2013

Authors:

Jin Hui Zhao, Xiao Hong Wang

Keywords:

AES, Encryption Media, Field-Programmable Gate Array (FPGA), MMS, Petalinux

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References

[1] Su Ma, Ji Wang. High speed implementation of AES algorithm based on FPGA,. Microcomputer information 1008-0570(2009)09-2-0127-02.

Google Scholar

[2] Yudong Cai, Xiaolang Yan. A High Speed Implementation of AES,. Master Dissertation of Zhejiang University.

Google Scholar

[3] Wang Youren, Wang Li, Yao Rui, Zhang Zhai, Cui Jiang. Dynamically reconfigurable encryption system of the AES, Wuhan University Journal of Natural Sciences, 2006, Vol. 11 (6).

DOI: 10.1007/bf02831822

Google Scholar

[4] B.D.C.N. Prasad, P.E.S.N. krishna Prasad, P Sita Rama Murty, K Madhavi. A Performance Study on AES Algorithms, International Journal of Computer Science and Information Security, 2010, Vol. 8 (6), p.128.

Google Scholar

[5] Mohammad A. Musa, Edward F. Schaefer, Stephen Wedig. A SIMPLIFIED AES ALGORITHM AND ITS LINEAR AND DIFFERENTIAL CRYPTANALYSES, Cryptologia, 2003, Vol. 27 (2), p.148.

DOI: 10.1080/0161-110391891838

Google Scholar