The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB

Jing Chen; Chang Yin Liu; Xue Ping Li

doi:10.4028/www.scientific.net/AMR.791-793.2122

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 791-793The Design and FPGA Implementation of a Polyphase...

The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB

Abstract:

Polyphase FIR filters are applied in many practical Digital Signal Processing applications where the sampling rate needs to be changed. This paper focuses on the implementation of polyphase square root raised cosine (SRRC) FIR filter based on Field Programmable Gate Array (FPGA). The filter employs methods like filter's multiphase structure, symmetrical coefficients, I/Q channel multiplexing, pipeline addition and so on to design the SRRC filter. Compared with the traditional method, the designed FIR filter exhibits the advantages of high response speed and low hardware resource s consumption.

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Periodical:

Advanced Materials Research (Volumes 791-793)

Pages:

2122-2126

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.791-793.2122

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Online since:

September 2013

Authors:

Jing Chen, Chang Yin Liu, Xue Ping Li

Keywords:

Adder, FIR SRRC, I/Q Complex, Multiplier, Polyphase

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References

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