Research on Digital Signal Processing of Wireless Anti-Jamming Data Link Node Based on FPGA

Abstract:

Wireless anti-jamming data link was widely applied in modern electronic warfare environment recently. Anti-jamming function of wireless data link was realized by constantly changing the signal carrier frequency according to a specific pseudo-random sequence. Frequency switching time and bandwidth were the main factors of frequency hopping anti-jamming performance. With the development DDS technology, frequency switching time and bandwidth had been improved significantly. The hardware of anti-jamming data link node in this paper was composed of frequency synthesizer module and FPGA control module taking advantage of both DDS technology and FPGA. Frequency synthesizer module was under the control of FPGA to output appropriate frequency carrier signal. FPGA control module is designed in Quartus II software development platform environment. The frequency tuning and control of frequency synthesizer module output signal were operated through serial or parallel I/O ports. Two kinds of configuration mode were designed in FPGA control module: serial configuration mode and parallel configuration mode. Digital signal data process in serial configuration logic and parallel configuration logic of FPGA control module were studied especially. The main function of serial configuration logic and parallel configuration logic were realized to process the digital signal data under appropriate time sequence correctly. By the correct time sequence of reading and writing function, frequency synthesizer module worked well with FPGA control module. Simulation and experiment results showed that anti-jamming data link node outputted stable frequency carrier signals by the excellent processing of digital signal data transferred between FPGA control module and frequency synthesizer module.

• Periodical: Advances in Science and Technology (Volume 105)
• Pages: 167-171
• DOI: https://doi.org/10.4028/www.scientific.net/AST.105.167
• Online since: April 2021
• Authors: Yong Mao Cheng*, Tian Yu Li, Qiang Xu
• Keywords: Anti-Jamming Data Link, Digital Signal Data Process, Direct Digital Synthesis, FPGA

References

[1] Altera Corporation 2012 Cyclone IV Device Handbook Https: // www.altera.com.

[2] Device A.Inc. 2012 AD9915 data sheet Https: // www.analog.com.

[3] Li Y, Shirani R, St-Hilaire M 2012 Improving routing in networks of unmanned aerial vehicles: reactive-greedy-reactive Wirel Commun Mob Comput 12 1608–19.

DOI: 10.1002/wcm.2333

[4] Arafat M Y, Moh S 2019 A survey on cluster-based routing protocols for unmanned aerial vehicle networks IEEE Access 7 498–516.

DOI: 10.1109/access.2018.2885539

[5] Zhang G Q, Zhang G Q 2012 Communication network designing: transmission capacity cost and scalability Sci China Inf Sci 55 2454–65.

DOI: 10.1007/s11432-011-4407-4

[6] Tonnellier T, Leroux C, Le Gal B 2016 Lowering the error floor of turbo codes with CRC verication IEEE WirelCommun Lett 5 404–7.

DOI: 10.1109/lwc.2016.2571283

[7] ZHAO La,QI Quan,ZHANG Jun 2015 Signal Generation Method Based on High Speed DDS Chip AD9914 Radar and confrontation 4 29-32.

[8] Dai X, Zhan M, Yan B. 2016 Design of a DDS based frequency synthesizer IEEE International conference on Communication Problem-Solving 239-42.

DOI: 10.1109/iccps.2015.7454139

[9] Huang Guo-qing and Qiao Tian-xi 2011 Implementation of DS/FH communication intermediate frequency π/4-DQPSK modulation based on FPGA International Conference on Intelligent Control and Information Processing 233-7.

DOI: 10.1109/icicip.2011.6008238

[10] SHANG Y L, QU L 2016 Analysis for modeling electromagnetic characteristics of via in high-speed printed circuit board Advance in Information Sniennes and Service Sniennes 5 589-96.