[1]
Semiconductor Industry Association (SIA). The International Technology Roadmap for Semiconductors, Radio Frequency and Analog/Mixed-Signal Technologies Summary. 2013 Edition.
Google Scholar
[2]
Zahid Ali Khan Durrani, Single-Electron Devices and Circuits in Silicon World Scientific, pages – 285, (2009).
Google Scholar
[3]
J.J. Kim and K. Roy, Double gate-MOSFET subthreshold circuit for ultralow power applications IEEE Trans. on Electron Devices, Vol. 51, no. 9, p.1468–1473, (2004).
DOI: 10.1109/ted.2004.833965
Google Scholar
[4]
Paul L. McEuen, Michael S. Fuhrer, and Hongkun Park, Single-Walled Carbon Nanotube Electronics IEEE Trans. Nanotechnology, vol. 1, p.78–85, (2002).
DOI: 10.1109/tnano.2002.1005429
Google Scholar
[5]
M. Dragoman and D. Dragoman, Nano Electronics- Principles and Devices Artech House, Boston, London, 2nd edition, (2010).
Google Scholar
[6]
M.J. O Connell, Carbon Nanotubes: Properties and applications, Taylor and Francis Group, Boca Raton, FL, (2006).
Google Scholar
[7]
O'Connor, I., L. Junchen, F. Gaffiot, P. Fabien, CNTFET Modeling and Reconfigurable Logic-Circuit Design, IEEE Trans. On Circuits and Systems—I: Regular Papers, Vol. 54, no. 11, p.2365 – 2379 Nov. (2007).
DOI: 10.1109/tcsi.2007.907835
Google Scholar
[8]
Keshavarzian, P., Navi, K., Universal ternary logic circuit design through carbon nanotube technology, Int. J. Nanotechnology, 6, (10–11), p.942–953, (2009).
DOI: 10.1504/ijnt.2009.027557
Google Scholar
[9]
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi, CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits, IEEE Trans. Nanotechnology, vol. 10, no. 2, p.217–225, Mar. (2011).
DOI: 10.1109/tnano.2009.2036845
Google Scholar
[10]
Doostaregan, A. Navi, K., Design of energy-efficient and robust ternary circuits for nanotechnology IET Circuits Devices System, vol. 5, no. 4, p.285–296, (2011).
DOI: 10.1049/iet-cds.2010.0340
Google Scholar
[11]
Usmani FA, Hasan M. Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach. Microelectronics Journal 2010; 41: 395.
DOI: 10.1016/j.mejo.2010.04.011
Google Scholar
[12]
Gowri sankar PA, Udhayakumar K. Design and Analysis of Two Stage Operational Amplifier Based on Emerging sub-32nm Technology. Advanced Nanomaterials & Emerging Eng. Techn. (ICANMEET 2013) IEEE Int. Conf. 2013; pp.587-591.
DOI: 10.1109/icanmeet.2013.6609382
Google Scholar
[13]
Gowri sankar P. A, Udhayakumar K, A novel carbon nanotube field effect transistor based arithmetic computing circuit for low-power analog signal processing application. Procedia Technology 12 (2014) p.154 – 162.
DOI: 10.1016/j.protcy.2013.12.469
Google Scholar
[14]
Gowri sankar P. A, Udhayakumar K, A Novel Carbon Nanotube Field Effect Transistor Based Analog Signal Processing Circuits for Low-power Communication Systems Lecture Notes in Electrical Engineering, 298, 2014, pp.329-340.
DOI: 10.1007/978-81-322-1817-3_33
Google Scholar
[15]
Y. Matsuya and J. Yamada. 1 V Power Supply, Low-Power Consumption A/D Conversion Technique with Swing-Suppression Noise Shaping, IEEE Journal of Solid-State Circuits, 29(12): 1524-1530, December (1994).
DOI: 10.1109/4.340426
Google Scholar
[16]
C.J.B. Fayomi, G.W. Roberts, and M. Sawan. A 1-V, 10-bit Rail-to-Rail Successive Approximation Analog-to- Digital Converter in Standard 0. 18µm CMOS Technology, IEEE International Symposium on Circuits and Systems, pp. I460-I463, (2001).
DOI: 10.1109/iscas.2001.921892
Google Scholar
[17]
M. Waltari and K.A.I. Halonen. 1-V 9-Bit Piplined Switched-Opamp ADC, IEEE Journal of Solid-State Circuits, 36(1): 129-134, January (2001).
DOI: 10.1109/4.896237
Google Scholar
[18]
S. Mortezapour and E.K.F. Lee. A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process, IEEE Journal of Solid-State Circuits, 35(4): 642-646, April (2001).
DOI: 10.1109/4.839925
Google Scholar
[19]
A. Javey, J. Guo, Q. Wang, M. Lundstrom, and H. J. Dai, Ballistic carbon nanotube field-effect transistors, Nature, vol. 4, p.654–657, (2003).
DOI: 10.1038/nature01797
Google Scholar
[20]
R. Martel, V. Derycke, C. Lavoir, J. Appenzeller, K. K. Chan, J. Tersoff, and Ph. Avouris, Ambipolar Electrical Transport in Semiconducting Single-wall Carbon Nanotubes, Physics Review Letter, vol 87, p.256805 (4), (2001).
DOI: 10.1103/physrevlett.87.256805
Google Scholar
[21]
Javey, A., Guo J., Farmer, D., Wang, Q., Yenilmez, E., Gordon, R., Lundstrom, M., and Dai, H., Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays, Nanoletter, vol. 4, p.1319–1322, (2004).
DOI: 10.1021/nl049222b
Google Scholar
[22]
Javey, A., Tu, R., Farmer, D. B., Guo, J., Gordon, R. G., and Dai, H., High-performance n-type carbon nanotube field-effect transistors with chemically doped contacts, Nanoletter, vol. 5, p.345–348, (2005).
DOI: 10.1021/nl047931j
Google Scholar
[23]
Y. Duan, J.L. Juhala, Solution-based fabrication of p-channel and n-channel field-effect transistors using random and aligned carbon nanotube networks, Microelectronic Engineering, Volume 103, March 2013, Pages 18–21.
DOI: 10.1016/j.mee.2012.09.016
Google Scholar
[24]
J. Appenzeller, Carbon nanotubes for high performance electronics, Proceeding of IEEE 96 (2) p.206, (2008).
Google Scholar
[25]
Yoo, J. (2003). A TIQ based CMOS Flash A/D converter for System-On-Chip applications, Doctor of Philosophy Thesis, The Pennsylvania State University.
Google Scholar
[26]
A. Tangel, K. Choi, "The CMOS Inverter as a comparator in ADC Designs, Analog Integrated Circuits and Signal Processing, Vol. 24, pp.147-155, May (2004).
DOI: 10.1023/b:alog.0000024062.35941.23
Google Scholar
[27]
C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, A 6-bit 1. 2GS/s Low-Power Flash ADC in 0. 13µm Digital CMOS, IEEE Journal of Solid State Circuits, Vol. 40, no. 7, pages 1499-1505, July (2005).
DOI: 10.1109/jssc.2005.847215
Google Scholar
[28]
S. Sheikhaei, S. Mirabbasi, and A. Ivanov, An encoder for a 5GS/s 4-bit flash ADC in 0. 18ȝm CMOS, CCECE 2005, p.698–701, May (2005).
DOI: 10.1109/ccece.2005.1557025
Google Scholar
[29]
Timmy Sundström and Atila Alvandpour, A 2. 5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS, NORCHIP, 16-17 Nov. (2008).
DOI: 10.1109/norchp.2008.4738324
Google Scholar
[30]
D. Ghai, S. P. Mohanty, and E. Kougianos (2009), A 45nm Flash Analog to Digital Converter for Low Voltage High Speed System on Chips, in Proceedings of the 13th NASA Symposium on VLSI Design, CD-ROM Electronic Proceedings paper # 3. 1 pp.1-10.
Google Scholar
[31]
Guolei Yu and Liter Siek, Low-power 4-bit flash ADC for digitally controlled DC-DC converter, Integrated Circuits (ISIC), 13th International Symposium, p.605 – 608, 12-14 Dec. (2011).
DOI: 10.1109/isicir.2011.6131935
Google Scholar
[32]
Parvaiz Ahmad Bhat, Roohie Naaz Mir, Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADC, in Proceedings of International Conference on Advances in Computing Advances in Intelligent Systems and Computing vol. 174, pp.319-328, (2012).
DOI: 10.1007/978-81-322-0740-5_38
Google Scholar
[33]
S.S. Khot, Dr. P.W. Wani, Dr. M S Sutaone, Shubhang Tripathi, Design of a 45nm TIQ Conmparator for High Speed and Low Power 4-bit Flash ADC, in proceedings of International. confrence on Advances in Electrical & Electronics (ACEEE), vol. 2, no. 01, Feb (2011).
Google Scholar
[34]
J. Deng and H. -S. P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including non-idealities and its application-Part I: Model of the intrinsic channel region, IEEE Trans. Electron Device, vol. 54, no. 1 2, p.3186–3194, Dec. (2007).
DOI: 10.1109/ted.2007.909030
Google Scholar
[35]
J. Deng and H. -S. P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part II: Full device model and circuit performance benchmarking, IEEE Trans. Electron Device, vol. 54, no. 12, p.3195–3205, Dec. (2007).
DOI: 10.1109/ted.2007.909043
Google Scholar
[36]
(2008). Stanford University CNFET model Website. Stanford University, Stanford, C A [Online]. Available: http: /nano. stanford. edu/model_stan_cnt. htm.
DOI: 10.1093/gmo/9781561592630.article.50735
Google Scholar
[37]
El Shabrawy, K., Maharatna, K., Bagnall, D., Al-Hashimi, B.M.: Modeling SWCNT bandgap and effective mass variation using a Monte Carlo approach, IEEE Trans. Nanotechnology, 2010, 9, (2), p.184–193.
DOI: 10.1109/tnano.2009.2028343
Google Scholar
[38]
Shahidipour, H., Ahmadi, A., Maharatna, K.: Effect of variability in SWCNT-based logic gates,. Proceeding Int. Symp. on Integrated Circuits, Singapore, December 2009, p.252 –255.
Google Scholar