Design of the Technological Flow to Produce a Planar Variant of the Nothing on Insulator Device and its Tunneling Conduction

Abstract:

This paper starts from the leakage currents through the gates of the last MOSFET generations and propose a related structure, which can be inherently included as parasitic device in any future MOSFET sub-22nm or can be deliberated fabricated to induce its own behavior. This structure is abbreviated in this paper by p-NOI (planar-Nothing On Insulator) and it can be simply produced by the planar Si-technology. Its concept is derived from the NOI (Nothing On Insulator) concept, but replaces the vacuum with oxide. The conduction mechanism is based on a thin oxide tunneling, under the Fowler-Nordheim's law. The current flow occurs from a source to a lateral drain, without an inversion channel and without a lateral pn junction, as in the MOSFET case. A similar investigated device by other authors is a fabricated MIM (Metal-Insulator-Metal) structure, which is compared with the actual p-NOI simulation. Finally, a dual gate p-NOI device is investigated. The depletion-accumulation transition is captured by the static I-V static characteristics. Using two steps of oxide, of 2nm and 10nm, a second planar-NOI structure with three terminals was studied. The (G) terminal is associated to a Gate and the (S) terminal is associated to a Source of a Field Effect Transistor. Some particular applications as diode or transistor are emphasized versus the gate biasing regime.

• Periodical: Journal of Nano Research (Volume 60)
• Pages: 33-41
• DOI: https://doi.org/10.4028/www.scientific.net/JNanoR.60.33
• Online since: November 2019
• Authors: Cristian Ravariu*, Elena Manea, Cǎtǎlin Corneliu Pârvulescu, Dan Mihaiescu
• Keywords: Nanoscale, Simulations, Tunneling, Ultra-Thin Oxides

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