The Effect of Thermal Prestress on the Deformation of Micromirror Chip Embedded with Through-Silicon Vias

Abstract:

Article Preview

The thermal expansion mismatch problem for a chip due to temperature decrease from processing temperature to room temperature may cause residual stress inside the chip structure. The thermal prestress accumulated and may affect the chip reliability when the chip was subjected to the thermal loading again. In this paper, the effect of thermal prestress on the micromirror chip embedded with copper through-silicon vias (TSVs) was investigated by the finite element method. In analysis, the micromirror chip embedded with TSVs was analyzed first under thermal loading which resulted from temperature decrease between the stress free processing temperature and room temperature. This process produced a thermal prestress in the micromirror chip. The chip was then subjected to a heat source at the bottom while in operation and the heat transfer analysis was used to simulate this situation. Finally, the thermal stress analysis was carried out to obtain the deformation and the stress distribution in the chip. The results show that the thermal prestress had strong effect on the chip reliability and should be reduced as much as possible. This paper proposed a three steps analysis method to obtain the deformation and the stress distribution in the chip, in which the effect of thermal prestress on the chip reliability was evaluated effectively.

Info:

Periodical:

Key Engineering Materials (Volumes 462-463)

Edited by:

Ahmad Kamal Ariffin, Shahrum Abdullah, Aidy Ali, Andanastuti Muchtar, Mariyam Jameelah Ghazali and Zainuddin Sajuri

Pages:

563-568

Citation:

M. K. Yeh and C. L. Lu, "The Effect of Thermal Prestress on the Deformation of Micromirror Chip Embedded with Through-Silicon Vias", Key Engineering Materials, Vols. 462-463, pp. 563-568, 2011

Online since:

January 2011

Export:

Price:

$41.00

[1] H. M. Jeong, Y. H. Park, Y. C. Cho, J. Hwang, S. M. Chang, S. J. Kang, H. K. Jeong, J. O Kim and J. H. Lee: J. Micro/Nanolith. MEMS MOEMS, Vol. 7, No. 4 (2008), pp.0043003-13.

[2] C. Ataman and H. Urey: Proc. SPIE, Vol. 6993 (2008), pp.699303-8.

[3] T. L. Tang, C. P. Hsu, W. C. Chen and W. L. Fang: J. Micromech. Microeng., Vol. 20 (2010), pp.025020-8.

[4] A. Wolter, H. Korth, H. Schenk, H. Lakner: IEEE/LEOS International Conference, (2003), p.56.

[5] H. Miyajima: J. Microlith. Microfab. Microsyst., Vol. 3, No. 2, (2004), p.348.

[6] N. Ranganathan, K. Prasad, N. Balasubramanian, Z. Qiaoer and S. C. Hwee: IEEE Electronic Components and Technology Conference, (2005), p.343.

[7] J. Zhang, M. O. Bloomfield, J. Q. Lu, R. J. Gutmann and T. S. Cale: IEEE Trans. Semicond. Manuf., Vol. 19, No. 4, (2006), p.437.

[8] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan and T. C. Chai: IEEE Electronic Components and Technology Conference, (2008), p.1073.

[9] Release 11. 0 Documentation for ANSYS: Theory Reference, (2006).

[10] M. K. Yeh and T. M. Hong: Proceedings of the 4th Asia Pacific Conference on Transducers and Micro/Nano Technologies, APCOT 4, Tainan, Taiwan, ROC, (2008), Paper No. 295.

[11] B. Z. Hong and L. G. Burrell: IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part A, Vol. 20, No. 3, (1997), p.280.

[12] R. Liu, H. Wang, X. Li, G. Ding and C. Yang: J. Micromech. Microeng., Vol. 18 (2008), p.1.

[13] G. R. Blackwell, The Electronic Packaging Handbook, CRC Press, Boca Raton (2000).