Investigation of Silicon Lapping and Polishing Technique for Micro-Inertial Device

Zhang Long; Zhu Jian

doi:10.4028/www.scientific.net/KEM.503.334

Paper Titles

Design and Simulation for Tri-Axial Piezoresistive MEMS Accelerometer
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Emulated Analysis of the Preview-LQG Controller for Micromachined Tunneling Gyroscope
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Two Fabrication Schematics of Silicon Micro Perforated Panel Based on MEMS Technology
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Research on the Hydrophobicity of Black Silicon Based on Virtual Process
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Investigation of Silicon Lapping and Polishing Technique for Micro-Inertial Device
p.334

The Microfluid-Driven Control by Forced Wave
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Analysis and Simulation of Micro-Fluidic Inertial Switch
p.348

Experimental Study on a Small Flux, High Pressure Peristaltic Micropump
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Numerical Simulation of Multi-Physical Fields Coupling and Design of a Digital Microfluidics Chip
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HomeKey Engineering MaterialsKey Engineering Materials Vol. 503Investigation of Silicon Lapping and Polishing...

Investigation of Silicon Lapping and Polishing Technique for Micro-Inertial Device

Abstract:

The precision lapping and polishing Si wafer is presented. Three-step lapping Si wafer and two-step polishing Si wafer are adopted within this processing. The Al2O3 abrasive of 20μm, 9μm and 3μm is used to lap wafer, then precision polishing is done with lapping agent of CeO2 and SF1. The thickness of the Si wafer can be controlled accurately, the flatness can be controlled within 3μm, and the roughness can be controlled under 1nm. The stress can be decreased evidently, even the thickness of the Si wafer is thinned down to 60μm, it is still flat.

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Periodical:

Key Engineering Materials (Volume 503)

Pages:

334-338

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.503.334

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Online since:

February 2012

Authors:

Zhang Long, Zhu Jian

Keywords:

Flatness, Micro-Inertial Device, Precision Lapping, Precision Polishing, Roughness

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