Application of a Ag Ductile Layer in Minimizing Si Die Stresses in LDMOS Packages

Abstract:

Lateral Diffused Metal Oxide Semiconductors (LDMOS) normally have a Cu-W flange, whose CTE is matched to Si. Low cost Cu substrate material provides 2X high thermal conductivity, and along with a AuSi eutectic solder is recommended for optimal thermal performance. However, the CTE mismatch between Cu and Si can lead to failure of the semiconductor as a result of die fracture, due to thermal stresses developed during the soldering step of the manufacturing process. Introducing a Ag ductile layer is very important in minimizing such thermal stresses and preventing catastrophic failure of the semiconductor. Ag is a ductile material electroplated on the Cu substrate to absorb stresses developed during manufacturing due to the CTE mismatch between Si and Cu. The Ag layer thickness affects the magnitude of the resulting thermal stresses. This study attempts to measure the yield strength of the Ag layer, and examines the optimal layer thickness to minimize die stresses and prevent failure. The yield stress of the ductile layer deposited on a Cu flange was measured by nanoindentation. The Oliver and Pharr method was applied to obtain modulus of elasticity and yield depth of Ag. A finite element analysis of the package was performed in order to map die stress distribution for various ductile layer thicknesses. The analysis showed that increasing the ductile layer thickness up to 0.01 - 0.02 mm, decreases the Si die stresses.

• Periodical: Key Engineering Materials (Volume 605)
• Pages: 372-375
• DOI: https://doi.org/10.4028/www.scientific.net/KEM.605.372
• Online since: April 2014
• Authors: Roselita Fragoudakis*, Michael A. Zimmerman, Anil Saigal
• Keywords: Coefficient of Thermal Expansion (CTE), Ductile Layer, Lateral Diffused Metal Oxide Semiconductor (LDMOS), Nanoindentation, Oliver, Pharr Method, Thermal Stress

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