Materials Science Forum
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Materials Science Forum
Vol. 1129
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Vol. 1126
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Materials Science Forum
Vol. 1124
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Vol. 1122
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Materials Science Forum
Vol. 1121
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Materials Science Forum
Vol. 1119
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Materials Science Forum
Vol. 1118
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Materials Science Forum Vol. 1124
Paper Title Page
Abstract: Silicon-carbide-on-insulator (SiCOI) is a promising platform for photonic integrated circuits. However, the development of this new photonic platform is hindered by the lack of high-quality commercial SiC-on-insulator substrates. In this study, we present a demonstration of the transfer of a single crystalline semi-insulating 4H-SiC thin film on a SiO2 insulated substrate at 150 mm wafer scale using the Smart Cut™ technology. We describe the development of SiCOI substrates and their characterization at each key step of the process. In particular, we provide a detailed study of bow compensation related to the implanted SiC donor substrate. The quality of the transferred SiC layer was investigated as a function of the final annealing temperature applied. The optical indices of the bulk SiC were measured using spectroscopic ellipsometry, and an advanced model has been used to take into account the strong birefringence of the silicon carbide film. Finally, simulations were conducted to design a preliminary set of basic and advanced photonic devices.
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Abstract: In conventional machining of SiC wafers, material loss and sub-surface damage (SSD) of both the front and back surfaces are major issues. In this study, we focused on Dynamic AGE-ing® (DA), which is a sublimation-controlled process, and applied it to the total wafering process without any mechanical contact of both the front and back surfaces to explore the possibilities to reach the CMP-equivalent quality. DA process enables material lossless planarization of SiC wafers by applying a temperature gradient to achieve simultaneous etching and growth at the same rate on one and the other surfaces, respectively. To drive the planarization function for a multi-wire saw finished as-sliced wafer, as an example, a high-temperature regime above 2000 °C under an Ar background pressure higher than 1 kPa to suppress etching and growth rates was employed as the first step in the DA treatment. In this step, an effective annealing function arises where sublimation and recrystallization occur simultaneously through a sub-surface region on both sides of the wafer. Due to the active interchange of the surface and subsurface layer, a self-organizing planarization effect occurs on a macroscopic scale on both surfaces with the removal of SSD. The conventional DA processes were employed for the following microscopic flatness control. As a result, the roughness of the 6-inch as-sliced wafer was reduced to 0.7 nm on the Si-face and 2.0 nm on the C-face while maintaining the wafer thickness. This is the first promising result exhibiting the potential of thermal contactless treatment for next-generation wafer manufacturing by improving quality and cost.
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Abstract: A damage-free SiC wafer dicing method has been strongly required for practical applications of power devices. In this research, we propose water jet guided laser processing as a novel dicing method. Water jet guided laser processing, which uses a high-pressure fine water jet as waveguide, could generate no cracks or dislocations in crystal. In this paper, water jet guided laser grooving quality was evaluated to demonstrate there should be no chippings and basal plane dislocations. Scanning electron microscopic and X-ray topography observations were conducted. The results indicated the superiority of water jet guided laser dicing to a conventional dicing method.
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Abstract: High purity semi-insulating (HPSI) 4H-SiC wafers from different vendors have been studied by surface photovoltage spectroscopy (SPV). It is demonstrated that the surface photovoltage signal height can be used to discriminate between non-compensated and compensated material, and that the SPV signal is also proportional to the bulk resistivity, at least for non-compensated 4H-SiC material.
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Abstract: We verify experimentally to what extent the intensity of 3C-SiC TO peak in infrared reflectance spectrum can be used to estimate the thickness of extremely thin 3C-SiC epilayers on Si. The influence of several Si substrate characteristics (orientation, doping level, back-side surface preparation) on the peak calibration is discussed.
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