Materials Science Forum Vol. 1124

Abstract: We present results of epitaxial characterization and benchmarking of Silicon Carbide (SiC) epitaxial layers grown on both 6-inch commercially available SiC substrate and on SOITEC’s new generation SmartSiC^TM substrate. Multi wafer reactor was utilized to avoid run-to-run variation. Schottky Barrier Diodes (SBD) and electrical test vehicles were fabricated to extract ideality factor, barrier height and ohmic contact resistance for benchmarking.

Abstract: Mesa- and trench-patterned surfaces of 4H-SiC(0001) 4°off wafers were structured in macrosteps using Si melting in a SiC-Si-SiC sandwich configuration. Si spreading difficulties were observed in the case of trench-patterned samples while the attempts on mesa-patterned ones were more successful. In the latter case, parallel macrosteps were formed on both the dry-etched and unetched areas though these macrosteps rarely cross the patterns edges. The proposed mechanism involved preferential etching at Si-C bilayer step edges and fast lateral propagation along the [1120] direction.

Abstract: A novel approach for processing SiC wafers has been developed to grind then polish 150 and 200mm SiC wafers without lapping. The purpose of this work was to optimize the processing of SiC wafers sliced from boules to finished epi-ready wafers by grinding and chemical-mechanical polishing (CMP). Diamond vitrified wheels were used for coarse and fine grinding to correct the irregular shape of SiC wafers before reducing surface roughness by CMP. 4H-SiC wafers were sliced by diamond embedded/slurry wire saw and laser split techniques. Incoming wafer condition was seen to affect coarse grinding wheel performance depending on incoming surface roughness and shape. Wheel characteristics, including abrasive size, abrasive concentration, and bond structure, were adjusted to improve grinding efficiency based on incoming conditions. Coarse grinding wheels were able to reduce wafer total thickness variation to 3-5um and average surface roughness to 20-30nm (Ra). Fine grinding wheels were optimized to reduce total thickness variation (TTV) below 2um and surface roughness to 1-2nm Ra and peak-to-valley height of 20-30nm (Rt). Coarse and fine wafering time was less than 30 minutes total to remove 50 microns on both Si and C-face per wafer. Surface damage from grinding was removed after one hour of polishing each wafer by CMP, achieving surface roughness of 0.4nm Ra and 5-7nm Rt. The benefit of optimizing coarse and fine grinding of 150 and 200mm SiC wafers is demonstrated by producing flat wafers, which reduced overall processing time to prepare an epi-ready condition by CMP.

Abstract: SmartSiC™ products developed by Soitec in the past four years consist of a high quality monocrystalline silicon carbide (m-SiC) on the top of an ultra-low resistivity polycrystalline silicon carbide (p-SiC or poly-SiC), the interface being electrically conductive. These engineered substrates are intended to bring added value for vertical power devices compared to standard m-SiC, by leveraging the wide bandgap (WBG) properties of the m-SiC and the enhanced p-SiC properties of the base substrate. Thus, it is of paramount importance to understand and monitor the p-SiC properties. In this paper, we present its electrical resistivity, microstructure and texture measurements through SEM and EBSD, thermal conductivity through Laser Flash Anneal (LFA), and Young modulus measurements.

Abstract: A review of the specific characterisation techniques developed and customized for SmartSiC™ substrates is given. A focus is made on thermal characterization of this engineered structure as well as its beneficial features with regards to bipolar degradation.

Abstract: Porosifying the surface of a single crystalline silicon carbide (4H-SiC) wafer with the means of metal assisted photo chemical etching (MAPCE) promotes the adhesion of an electroplated nickel (Ni) layer. By utilizing a mechanical peel-off process, a Ni layer with tailored mechanical stress is peeled off such that also a thin layer of 4H-SiC is teared apart from the wafer as well.

Abstract: This work reports on the high-temperature reorganization behavior of single-crystalline porous 4H-silicon carbide (4H-SiC) thin foils. Porous 4H-SiC thin foils are realized via state-of-the-art photoelectrochemical etching in hydrofluoric (HF) acid solution enabling for the first time a released foil with a diameter of 2 inches. Subsequent annealing under inert gas atmosphere and comparison between samples suggests that a temperature of 1500 °C allows for various degrees of compactification across the foil surface, whereas at 1600 °C single crystallinity can be preserved.

Abstract: Since SiC is hard and brittle, dicing by normal grinding process not only requires a long time for processing, but also reduces chip strength due to microcracks. The use of highly efficient and damage-free etching with high-pressure plasma as a chemical processing method for dicing rather than mechanical processing was investigated. The results of groove processing using a combination of a metal mask with slit-like apertures and plasma etching with high-pressure SF₆ plasma showed that the processing speed decreased with decreasing slit width and increasing groove depth. The results of electrostatic field calculations suggest that this is due to a decrease in plasma intensity caused by electric field decreasing.

Abstract: SiC-on-Insulator (SiCOI) structures fabricated using the Smart Cut™ technique can be of great interest in order to probe the properties of a silicon carbide (SiC) transferred layer, by electrically insulating it from the receiver substrate. In this study, we report the fabrication of such a SiCOI structure using a SiC receiver, as well as its electrical and TEM characterization after high temperature annealing. We highlight a decrease of the transferred layer electrical resistivity with increasing annealing temperature, due to doping reactivation and electron mobility enhancement. After low temperature annealing (1200°C to 1400°C), deep acceptor levels, possibly located in a damaged region near the substrate’s surface, might be responsible of a non negligible electrical compensation. Beyond 1400°C however, the transferred SiC crystal is healed and electron transport is only subjected to shallow nitrogen ionization.