Current Gain Stability of SiC Junction Transistors Subjected to Long-Duration DC and Pulsed Current Stress

Siddarth G. Sundaresan; Brian Grummel; Ranbir Singh

doi:10.4028/www.scientific.net/MSF.858.929

Paper Titles

Modelling of 4H-SiC VJFETs with Self-Aligned Contacts
p.913

Conduction Loss Reduction for Bipolar Injection Field-Effect-Transistors (BIFET)
p.917

A 500 °C Monolithic SiC BJT Latched Comparator
p.921

Design Impact on the Static and Short-Circuit Characteristics of SiC-SIT with Non-Uniformly Doped Channel
p.925

Current Gain Stability of SiC Junction Transistors Subjected to Long-Duration DC and Pulsed Current Stress
p.929

Comparison of Energy Losses in High-Current 1700 V Switches
p.933

6.5 kV n-Channel 4H-SiC IGBT with Low Switching Loss Achieved by Extremely Thin Drift Layer
p.939

An Analysis of Forward Conduction Characteristics of Ultra High Voltage 4H-SiC N-IGBTs
p.945

Electro-Thermal TCAD Model for 22 kV Silicon Carbide IGBTs
p.949

HomeMaterials Science ForumMaterials Science Forum Vol. 858Current Gain Stability of SiC Junction Transistors...

Current Gain Stability of SiC Junction Transistors Subjected to Long-Duration DC and Pulsed Current Stress

Abstract:

The current gain stability of a second generation of 1200 V rated SiC Junction Transistors (SJTs) under long-term DC and pulsed current operation is investigated. A 1000-hour long, 200 A/cm² DC current stress results in a ≈ 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. The same amount of stress charge applied as a pulsed current in lieu of DC current results in similar extent of β degradation for the Gen-II SJTs. The pulsed current stressing is conducted at frequencies ranging from 50 kHz to 200 kHz, at a fixed duty cycle of 0.5.