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Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

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Abstract:

In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode.

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Periodical:

Nano Hybrids (Volume 3)

Pages:

93-113

DOI:

https://doi.org/10.4028/www.scientific.net/NH.3.93

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Online since:

January 2013

Authors:

Arash Dehzangi, Farhad Larki, Jumiah Hassan, Sabar D. Hutagalung, Elias B. Saion, Mohd N. Hamidon, A. Makarimi Abdullah, Alireza Kharazmi, Sanaz Mohammadi, Burhanoddin Y. Majlis

Keywords:

Atomic Force Microscope (AFM), Double Gate (DG), Junction-Less Silicon Nanowire Transistor (JLSNWT), Local Anodic Oxidation (LAO), Silicon-on-Insulator (SOI), Single Gate (SG)

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