Cleaning Requirement in the Thinning Module for 3D-Stacked IC (3D-SIC) Integration

Kurt Wostyn; Ming Zhao; Hu Shan Cui; Patrick Laermans; Anne Jourdain; Greet Verbinnen; Herbert Struyf; Steven de Strycker; Martine Claes; Youssef Travaly; Leonardus Leunissen

doi:10.4028/www.scientific.net/SSP.187.265

Paper Titles

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Wet Clean Induce Pattern Collapse Mechanism Study
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High Efficiency Single Wafer Cleaning for Wafer Bonding-Based 3D Integration Applications
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Cleaning Requirement in the Thinning Module for 3D-Stacked IC (3D-SIC) Integration

Abstract:

Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.

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Periodical:

Solid State Phenomena (Volume 187)

Pages:

265-268

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.187.265

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Online since:

April 2012

Authors:

Kurt Wostyn, Ming Zhao, Hu Shan Cui, Patrick Laermans, Anne Jourdain, Greet Verbinnen, Herbert Struyf, Steven de Strycker, Martine Claes, Youssef Travaly, Leonardus Leunissen

Keywords:

3D-SiC, Dicing, Edge Trimming, Grinding, Particle Contamination

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