Ultra Clean Processing of Semiconductor Surfaces X

Paper Title Page

Authors: Marc M. Heyns
Abstract: The megasonic cleaning efficiency is evaluated as a function of the angle of incidence of acoustic waves on a Si wafer. Acoustic Schlichting streaming alone is not able to remove nanoparticles smaller than 400 nm. It is shown that oscillating or collapsing behavior of bubbles are responsible for removing nanoparticles smaller than 400 nm during a cleaning process with ultrasound. Optimal particle removal efficiency is obtained around the angle of acoustic transmission of the silicon wafer.
3
Authors: W. Melitz, J.B. Clemens, J. Shen, E.A. Chagarov, S. Lee, J.S. Lee, J.E. Royer, M. Holland, S. Bentley, D. McIntyre, I. Thayne, R. Droopad, A.C. Kummel
Abstract: The megasonic cleaning efficiency is evaluated as a function of the angle of incidence of acoustic waves on a Si wafer. Acoustic Schlichting streaming alone is not able to remove nanoparticles smaller than 400 nm. It is shown that oscillating or collapsing behavior of bubbles are responsible for removing nanoparticles smaller than 400 nm during a cleaning process with ultrasound. Optimal particle removal efficiency is obtained around the angle of acoustic transmission of the silicon wafer.
9
Authors: Roger Loo, Laurent Souriau, Patrick Ong, Karine Kenis, Jens Rip
Abstract: Further improving complementary metal oxide semiconductor (CMOS) performance beyond the 15 nm generation likely requires the use of high mobility materials like Ge for pMOS devices. However, Ge pMOS devices made in relaxed Ge do not outperform current state of the art uni-axially strained Si pMOS devices. This explains the current interest in compressively strained Ge like bi-axially strained Ge grown on top of SiGe Strain Relaxed Buffers. From a device integration point of view, the surface smoothness of the strained Ge layer is an important parameter which has so far not widely been reported in literature, in contrast to other parameters like the material quality (crystallinity) and the threading dislocation density. In this paper we report the post-CMP and pre-epi cleans which are required to obtain contamination free SiGe surfaces to enable defect free strained Ge growth without reoccurrence of the surface roughening. We will demonstrate the epitaxial growth of fully strained 20 nm thick Ge epitaxially grown on top of SiGe Strain Relaxed Buffers with 85% Ge with a surface roughness as low as 1.6 Å (as measured on areas of 10×10 µm2).
15
Authors: Masayuki Wada, H. Takahashi, James Snow, Rita Vos, Thierry Conard, Paul W. Mertens, H. Shirakawa
Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.
19
Authors: Sonja Sioncke, Claudia Fleischmann, Dennis Lin, Evi Vrancken, Matty Caymax, Marc Meuris, Kristiaan Temst, André Vantomme, Matthias Müller, Michael Kolbe, Burkhard Beckhoff
Abstract: The last decennia, a lot of effort has been made to introduce new channel materials in a Si process flow. High mobility materials such as Ge need a good gate stack passivation in order to ensure optimal MOSFET operation. Several routes for passivating the Ge gate stack have been explored in the last years. We present here the S-passivation of the Ge gate stack: (NH4)2S is used to create a S-terminated Ge surface. In this paper the S-treatment is discussed. The S-terminated Ge surface is not chemically passive but can still react with air. After gate oxide deposition, the Ge-S bonds are preserved and an adequate passivation is found for pMOS operation.
23
Authors: Rita Vos, Sophia Arnauts, Thierry Conard, Alain Moussa, Herbert Struyf, Paul W. Mertens
Abstract: In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.
27
Authors: Joel Barnett, Richard Hill, Prashant Majhi
Abstract: The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.
33
Authors: Annamaria Votta, Francesco Pipia, Enrica Ravizza, Simona Spadoni, Silvia Rossini, Lucilla Brattico, Mauro Alessandri
Abstract: GST is an alloy composed by Ge, Sb, Te whose importance is increasing more and more in semiconductors manufacturing due to its usage in Phase Change Memories (PCM) architecture, as a charge storage element. As a consequence its integration in PCM architectures requires a deeper understanding of the effect that commonly used wet cleanings may have on the surface of the alloy.
37
Authors: Nick Valckx, Daniel Cuypers, Rita Vos, Harold Philipsen, Jens Rip, Geert Doumen, Paul W. Mertens, Marc M. Heyns, Stefan De Gendt
Abstract: Following Moores scaling law, the transistor source and drain area become shallower and higher doped regions. As a consequence the limitations of substrate and dopant loss during cleaning become more stringent. For a better understanding, highly B, As and P doped blanket substrates, either prepared by ion implantation or by EPI growth, are studied. Substrate and dopant loss as a function of time and different HF etching conditions is monitored by Inductively Coupled Plasma Mass Spectrometry (ICP-MS) and additional techniques like Spectroscopic Ellipsometry (SE), .... It is shown that in general, the Si etching is dependent of the position of the Fermi level. More remarkably, the junction (4 nm) of a non-annealed heavily As or P doped substrate is completely removed after less than 20 min of etching in HF. This process is related to enhanced etch rates because of the amorphization of the substrate.
41

Showing 1 to 10 of 81 Paper Titles