Solid State Phenomena Vol. 187

Abstract: NMP is a commonly used solvent for removing positive photoresist in 3D applications, especially in electroplating and (micro-) bumping. However, the negative photoresists are more and more preferred in these applications. Unfortunately, NMP is inefficient for negative photoresist and it is not considered in Europe as an ESH solvent anymore. In this paper a comparative study was carried out in order to identify a solvent that is ESH friendly and a one-size-fits-all solution for stripping negative-tone and thick positive-tone photoresist (2-22 μm) for (micro-) bumping, electroplating and TSV etch applications. The study was performed at tool level.

Abstract: Tungsten importance in semiconductor manufacturing is renewed more and more due to its usage not only as metallization for plugs, but also in metal gates architectures. As the scaling down of the devices is becoming aggressive, the metal interfaces become more critical. Hence, a deeper understanding of the evolution of the W surface after wet cleaning processes is becoming increasingly more important.

Abstract: The use of integration of copper interconnects in semiconductor devices has greatly advanced the development of integrated circuits and has enabled ever higher device densities. Unfortunately the oxides of copper are poorly suited to semiconductor manufacture. As Cu (I) and Cu (II) oxides are not self-limiting they can pose serious issues from a cleaning and queue time management perspective. In both post-etch and post-CMP cleaning applications it is critical that both types of Cu oxide are removed without damage to either Cu or the dielectric. With the most advanced sub 32nm nodes simply removing the oxides is not sufficient; their re-growth must also be prevented using surface passivation.

Abstract: Cu post-CMP clean is important to keep both Cu and low-k dielectric clean after polishing. In this paper, two Cu post-CMP clean solutions are analyzed in electrochemical, physical and electrical characterizations, based on the material and integration scheme of imec 65nm platform. It is shown that the combination of these two PCMP clean solutions can achieve both reasonable cleaning efficiencies and reliable low-k dielectric lifetime.

Abstract: A novel wet cleaning formulation approach was developed with a TiN etch rate of more than 30 Å/min at room temperature and more than 100 Å/min at 50°C. The chemicals are compatible with Cu and low-k materials, and are suitable for Cu dual damascene interconnect 28 nm and smaller technology node applications. The chemicals offer a route to in situ controlled TiN pullback or even complete removal of the TiN mask during the cleaning process in single wafer tool applications. The chemicals do not contain NH₄OH or TMAH and so are very user-friendly.

Abstract: Plasma dry etching processes are commonly used to fabricate sidewalls of trenches and vias for copper / low-k dual damascene devices. Typically, some polymers remain in the trench and at the via top and sidewall. Other particulate etch residues are may remained in the bottom and on the sidewalls of vias. Generally, the particulate consists of mixtures of copper oxide with polymers. The polymers on the sidewalls and the particulate residues at the bottom of vias must be removed prior to the next process step. Small amounts of polymer are intentionally left on the sidewalls of trenches and vias during the etching in order to achieve a vertical profile and to protect the low-k materials under the etching mask. Until now, the industry has relied mainly on organic solvent containing mixtures to clean etch / ash residues from such devices. The effectiveness of available residue removers varies with the specific process and also depends on which new integration materials are used. New materials typically include Cu, TaN, low-k dielectrics and others [1-. Solvent content is thought to aid the removal of polymer residues and particulates produced during plasma dry etching processes. Therefore, in the past we have used a residue remover which contains DMAC (dimethylacetamide). But the use of DMAC is banned in microelectronic fabrication facilities in Europe because of its toxicity. Thus we wanted to find and evaluate a DMAC-free residue remover for removing polymer residues while maintaining high selectivity to the copper and ILD films.

Abstract: Mallinckrodt Baker, Inc. (MBI) has developed an aqueous fluoride-based cleaner (AFC1) that shows improved ultra-low k (ULK) and cobalt tungsten phosphide (CoWP) compatibility over dilute hydrofluoric acid (dHF) and a simple solvent based cleaner (SFC1). Performance and compatibility testing was performed with beaker tests at MBI and on 45 nm wafers by GLOBALFOUNDRIES. Our results indicate that AFC1 may be a good alternative to dHF for future Cu technologies.

Abstract: Pattern collapse phenomenon was first time observed in BEOL application with the integration of ultra low-k film scheme. With the dimension and pitch shrinkage, the pattern collapse defects are getting worse during wet clean process. In this study, the line collapse defects can be significantly reduced by adding surfactant solution to the rinse liquid. Moreover, higher aspect ratio (>4) will also deteriorate the collapse window. In addition, the kink or bowing trench profile will induce localized stress at the interface. Accordingly, optimization of both wet clean and dry etch process are the successful keys to solve line collapse issue toward future generation and beyond.

Abstract: The number of consumer products requiring 3D stacked IC (3D SIC) is growing, and volume output is expected to start between 2011 and 2013. R&D centers and production sites are addressing the remaining obstacles to production for these new technologies. To enable fast production ramp, there is urgency to get enablers in place, including advanced, dedicated process control methods. Using an innovative high throughput inspection technology, we show ways to control future 3D SIC production lines, getting data from 100% of the wafers and providing defect classification for yield management.

Abstract: Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.