Solid State Phenomena Vol. 187

Abstract: The photovoltaic industry has maintained a rapid growth rate of more than 46% over the last 15 years. At the same time, the price of PV modules have continuously decreased to a point where PV is now at grid parity on the customer side of the meter in geographic areas with high incentives combined with high solar irradiation or high electricity price. The rapid growth rate of the PV industry is expected to continue and even accelerate as the regions with grid parity spread to more parts of the developed world. This is due to a combined reduction in the price of PV modules and an increase in the price electricity. Among all the different PV technologies, crystalline silicon solar cells have maintained a strong dominance of more than 82.5%. Thanks to extensive studies of silicon material properties, mechanisms of carrier recombination and the development of ultra-clean processing, the efficiency of silicon solar cells have reached more than 22% in large volume production and 25% in laboratory, and is approaching the theoretical maximum efficiency of silicon cells of about 29%.

Abstract: Emitter formation of crystalline silicon solar cells by inline diffusion can be affected by non-uniformities in dopant deposition prior to the furnace due to insufficient wetting of hydrophobic surfaces. The impact of dissolved ozone treatment after texturing has been investigated with respect to the possibility of improving the emitter formation with a low cost process enhancement. The chemically grown thin oxide improves wetting capability without modification of other surface characteristics that can impact cell efficiency. It could be shown that already low concentrations of ozone in UPW prior to phosphorus doping improve the sheet resistance uniformity on Cz-Si and multi-crystalline Si solar cells between 30 and 100 % compared to HF last treated ones.

Abstract: Simple two-step wet-chemical cleans composed of an oxidizing step with in water dissolved ozone followed by an etching step have been studied for high-efficient hetero-junction silicon solar cell applications. For this purpose flat Si (111) samples passivated with amorphous silicon have been investigated. The effect of nanoroughness of the crystalline silicon surface on the minority carrier lifetime is shown. An influence of the storage time between cleaning and a-Si:H deposition was found and can partly be attributed to changes in surface roughness and native oxide growth.

Abstract: In thin film photovoltaic silicon stacks, the sun facing contact needs to be transparent and textured. Typically transparent metal oxides are used for this purpose. When using sputtered ZnO as the transparent conducting contact typically an acid etch is used to texture etch the surface. This texturing enables light trapping in the cell and greatly enhances the photoresponse. Traditionally dilute HCl has been used for this purpose. In this paper we present the work on a novel etchant for this purpose consisting of HNO₃ and Acetic Acid. This greatly enhances the texturing and hence the light trapping in the cell.

Abstract: The new texture process Textur+ gives an increased efficiency and wafer yield compared to the standard UKN texture. This is achieved by adding a third acid, H₂SO₄, to the composition. The improvements are already proven for bath life times of 100,000 wafers. Furthermore we present first data on a further improved texture that allows reducing the reflectivity drastically. Therefore it is expected to improve the efficiency further with this process.

Abstract: The acidic texture bath that is commonly used in crystalline silicon solar cell manufacturing is a mixture of HF/HNO₃/H₂O [. While the influences of metal contamination on silicon wafer surfaces as well as several cleaning methods were intensively investigated in the previous 30 years [ the effect of metal contaminations in texturisation baths has not yet been studied intensively. There are two categories of contaminations:

Abstract: Solar cells employing heterojunction emitters of amorphous silicon (a-Si) on a monocrystalline silicon (c-Si) substrate have demonstrated high efficiencies without requiring high-temperature processing [. An example of such a cell structure is shown in Figure 1. It has been found that the cell efficiency can be boosted by inserting a thin undoped (intrinsic) a-Si layer between the a-Si emitter and the c-Si substrate. The thin intrinsic layer provides very good passivation of interface defects, thus reducing the surface recombination velocity.

Abstract: Amorphous/crystalline silicon heterojunction solar cells are commonly made by low temperature deposition of front and back side thin films on bare H-passivated Si wafers, obtained by HF last processes. This work discusses the impact of HF last step parameters on cell performance, considering textured and cleaned Si (100) wafers. A complete native oxide removal is mandatory and achieved in a short time (< 5 min) by HF concentration higher than 1% (by weight). Above 1%, surface passivation and cells performance slightly increases with the concentration. The best process time is found to be the minimum time to deoxidize textured wafers, as seen by a good dewetting. For [H > 2% this is less than 1 min. Longer process times slightly degrade surface passivation. Post rinse and drying, provided they do not reoxydize the surface, were seen to have no impact. The delay between the HF last and deposition steps is critical and depends on the efficiency of the cleaning before the HF last. With a high performance cleaning, leading to a very good surface passivation (< 10 cm/s surface recombination velocity), 30 min delay has no impact and 90 min leads to about 5% relative degradation of cell performance. Regarding the HF cleanliness, HCl spiking is an efficient way to enhance robustness of surface passivation keeping < 10 cm/s values when the metallic contamination, including Cu, is in the sub 50 ppb range.

Abstract: The dominance of crystalline silicon (Si) in photovoltaics can be ascribed partly to the extensive knowledge about this material, which has been accumulated in microelectronics technology. Methods to passivate Si interfaces, which were developed for microelectronic device technologies, have been extended to solar cell manufacturing in the past. These methods, however, have been optimised for polished substrates, and do not work so effective with textured surfaces, which commonly used in the fabrication of high efficiency Si solar cells to enhance anti-reflection properties.

Abstract: Texturing and polishing crystalline silicon in the PV industry are both time consuming and inefficient, the need for a streamlined solution is prevalent. To obtain high conversion efficiency surface decoupling is needed, one side0 of the wafer is ideally textured while the other is completely polished. The standard industrial process results in a total silicon loss of 40μm and a complete surface decoupling cycle time in the order of an hour from an as cut until diffusion ready. For an industrial wafer thickness of 180μm more than 20% of the silicon is lost. In addition to silicon loss, there are multiple wet processing steps needed for decoupling which are time consuming and hinder the high throughput manufacturing needed to achieve the ultimate goal of a low per watt peak price. The technique is proposed in this paper decouples the front and rear surfaces and utilizes in only one wet process step for both texturing and polishing. This process simplification leads to significant savings by decreasing costly cycle time, saving consumables and reducing the amount of silicon loss.