Solid State Phenomena Vol. 187

Abstract: HF vapor etching using thin Al₂O₃ film as etch stop material was studied. It was found that behavior of Al₂O₃ film in HF vapor can not be predicted from the blanket film studies only but it is important to use samples that resemble closely real process conditions instead. Resistivity of Al₂O₃ against HF vapor depends on whether a SiO₂ was etched on top of it or not. Other affecting factors are the thickness of the Al₂O₃ film, HF vapor process, stress of the oxide on top of it as well as topography under it. Even very thin 3 nm Al₂O₃ film resist HF vapor if no SiO₂ film is etched on top of it and etch process is slow enough.

Abstract: The present study aims at polysilicon material fill-in at re-entrant profile at flash memory product. The void was observed after polysilicon fill-in. In order to prevent the void formation, the multi-step process of deposition wet-etching deposition (DWD) method was evaluated. The DWD method is found to play beneficial roles in achieving void-free in the floating gate. The high concentration of NH₄OH in APM was choosing for wet etching solution. Scanned electron microscopy (SEM) and transmission electron microscopy (TEM) were employed to measure the polysilicon thickness and cross-section profile of device.

Abstract: We report in this work some process optimization effort in performing poly silicon removal for replacement gate process integration. Successful wet poly silicon removal after dummy gate patterning is not only conditioned by suitable process conditions during wet removal but is also impacted by process steps prior to gate removal A thorough evaluation of the impact on poly removal from dopants or contaminants introduced in the poly silicon by previous processing is done, resulting in an optimized integration flow with successful poly removal. This work also shows that use of diluted TMAH chemistry instead of diluted ammonia in performing poly silicon removal provides better ability in removing poly silicon especially in narrow gate structures.

Abstract: Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.

Abstract: The present work reports some approaches to reduce the static charge defects induced during single wafer cleaning process. Increase conductivity of DIW with CO₂, adding backside rinse and IPA drying sequence optimization were evidenced to be effective by surface potential difference with Quantox tool. TEM and EELS were also used for analysis of volcano-like discharge defects.

Abstract: In dual gate process, wet strip is an important procedure to remove the photoresist. Two wet strip methods of spinning-dry and batch type were evaluated in this study. Several methods were applied to measure the surface charging density [1, 2]. The Quantox system has been well known as an inline tester with noncontact measurement such as surface voltage, surface photo voltage (SPV), flatband voltage, surface barrier high, minority carrier diffusion length, recombination life time, generation life time, and et. al [3-6]. It is an useful in-line monitor equipment for oxide quality evaluation.

Abstract: The static electricity of wet clean was characterized by contactless surface voltage measurement on silicon oxide dielectric in this study. The paper shows surface static charge at wafer center caused by a single wafer spin cleaning tool. Deionized water (DIW) rinse was verified as the critical step of inducing static charge. It was demonstrated by metal oxide semiconductor (MOS) capacitor that such serious dielectric static charge would degrade gate oxide integrity (GOI). With dissolved CO₂ to lower DIW resistance, surface static charge at wafer center is reduced and degraded GOI is restored as a result.

Abstract: In this paper, we studied stiction behavior of HAR pattern (line and space pattern) dependence on adhesion force with surface tension of drying liquid and surface contact angle. Surface tension effect was evaluated with various drying liquids such as IPA, ethanol and HFE (hydrofluoroether) chemical. Patterns treated by dHF, APM and surface modifier were introduced to investigate dependence of pattern collapse on contact angle. The high temperature D.I. water rinse followed by high temperatures drying using liquid with low surface tension was a most effective. Furthermore, surface modification method using HMDS (hexamethyldisilazane) chemical was also effective.

Abstract: Displacing the water remaining on a wafer surface by using condensed IPA improves the effectiveness of IPA-based drying techniques. Although this drying technology has been used for years, recent device technologies have needed extremely high-performance drying processes. We characterized an IPA adsorption phenomenon on a wafer surface by using the batch cleaning system and determined the appropriate drying conditions. Our results revealed that the IPA supply rate had a great influence on watermark formation. This can be prevented by increasing the IPA supply rate because the rapid increase of IPA concentration in the remaining water on wafer surface suppresses the dissolution of silicon into water. Through both understanding of an IPA adsorption on a wafer surface and control of the drying condition, an ultra-clean and IPA-saving drying process with a watermark-free performance for future device technologies can be achieved.

Abstract: We performed two experiments on resist-coated wafers. In the measurement of the resist-wafer adhesivity, we confirmed that it is significantly increased by an HMDS layer in between. In the resist-removal experiment using steam-water mixed spray, we found that the area of resist removal is limited within the area of spray application if HMDS is used, otherwise the former can be larger than the latter. These results suggest that the resist removal from a wafer surface by steam-water mixed spray is essentially a peel-off process.