Poly-Silicon Wet Removal for Replacement Gate Integration Scheme: Impact of Process Parameters on the Removal Rate

Farid Sebaai; Anabela Veloso; Martine Claes; Katia Devriendt; Stephan Brus; Philippe Absil; Paul W. Mertens; Stefan De Gendt

doi:10.4028/www.scientific.net/SSP.187.53

Paper Titles

Effect of Wet Cleanings on GST Surface: XPS Characterization
p.37

Study of the Etching Mechanism of Heavily Doped Si in HF
p.41

Study on Al₂O₃ Film in Anhydrous HF Vapor
p.45

Deposition Wet-Etching Deposition (DWD) Method for Polysilicon Gate Fill-In at Flash Memory
p.49

Poly-Silicon Wet Removal for Replacement Gate Integration Scheme: Impact of Process Parameters on the Removal Rate
p.53

A Hybrid Dry-Wet Approach for Removal of a Dummy Polysilicon Gate in a Replacement Metal Gate Scheme
p.57

Static Charge Induced Damage during Lightly Doped Drain (LDD) by Single Wafer Cleaning Process
p.63

Surface Charging Induced Gate Oxide Degradation
p.67

Investigation of Wet Clean Induced Dielectric Surface Static Charge and its Impact on Gate Oxide Integrity
p.71

HomeSolid State PhenomenaSolid State Phenomena Vol. 187Poly-Silicon Wet Removal for Replacement Gate...

Poly-Silicon Wet Removal for Replacement Gate Integration Scheme: Impact of Process Parameters on the Removal Rate

Abstract:

We report in this work some process optimization effort in performing poly silicon removal for replacement gate process integration. Successful wet poly silicon removal after dummy gate patterning is not only conditioned by suitable process conditions during wet removal but is also impacted by process steps prior to gate removal A thorough evaluation of the impact on poly removal from dopants or contaminants introduced in the poly silicon by previous processing is done, resulting in an optimized integration flow with successful poly removal. This work also shows that use of diluted TMAH chemistry instead of diluted ammonia in performing poly silicon removal provides better ability in removing poly silicon especially in narrow gate structures.

You might also be interested in these eBooks

Ultra Clean Processing of Semiconductor Surfaces X

View Preview

Info:

Periodical:

Solid State Phenomena (Volume 187)

Pages:

53-56

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.187.53

Citation:

Cite this paper

Online since:

April 2012

Authors:

Farid Sebaai, Anabela Veloso, Martine Claes, Katia Devriendt, Stephan Brus, Philippe Absil, Paul W. Mertens, Stefan De Gendt

Keywords:

Contaminant Species, Diluted Ammonia, Diluted TMAH Solution, Dopant, Poly-Silicon, Poly-Silicon Opening, Replacement Gate

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] K. Mistry, A 45nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging, IEEE IEDM Tech. Dig, p.247 (2007).

Google Scholar

[2] C. Auth, 45nm high-k + metal gate strain enhanced transistors, IEEE VLSI Tech. Dig, p.128 (2008).

DOI: 10.1109/cicc.2008.4672101

Google Scholar

[3] P. Packan, High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors, IEEE IEDM Tech. Dig, p.659 (2009).

Google Scholar

[4] X. Gregory Zhang, Electrochemistry of silicon and its oxide (2001), pp.308-309.

Google Scholar

[5] A. Veloso, Strain enhanced FUSI/HfSiON technology with optimized CMOS Process Window. VLSI Technology (2007).

Google Scholar

[6] F. Sebaai, Poly silicon etch with diluted ammonia: application to replacement gate integration ammonia, Solid State Phenomena Vols, 145-146 (2009), pp.207-210.

DOI: 10.4028/www.scientific.net/ssp.145-146.207

Google Scholar