Achieving Ultra-Shallow Junctions in Future CMOS Devices by a Wet Processing Technique

Joel Barnett; Richard Hill; Prashant Majhi

doi:10.4028/www.scientific.net/SSP.187.33

Paper Titles

Optimized Post-CMP and Pre-Epi Cleans to Enable Smooth and High Quality Epitaxial Strained Ge Growth on SiGe Strain Relaxed Buffers
p.15

Cleaning and Surface Preparation for SiGe and Ge Channel Device
p.19

S-Passivation of the Ge Gate Stack Using (NH₄)₂S
p.23

Wet Chemical Cleaning of InP and InGaAs
p.27

Achieving Ultra-Shallow Junctions in Future CMOS Devices by a Wet Processing Technique
p.33

Effect of Wet Cleanings on GST Surface: XPS Characterization
p.37

Study of the Etching Mechanism of Heavily Doped Si in HF
p.41

Study on Al₂O₃ Film in Anhydrous HF Vapor
p.45

Deposition Wet-Etching Deposition (DWD) Method for Polysilicon Gate Fill-In at Flash Memory
p.49

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Achieving Ultra-Shallow Junctions in Future CMOS Devices by a Wet Processing Technique

Abstract:

The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.

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Periodical:

Solid State Phenomena (Volume 187)

Pages:

33-36

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.187.33

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Online since:

April 2012

Authors:

Joel Barnett, Richard Hill, Prashant Majhi

Keywords:

InGaAs, Monolayer Doping, Sulfur, Ultra-Shallow Junctions

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