Evaluation of Wafer Drying Methods for GIGA-LEVEL Device Fabrication

Gyu Hyun Kim; Geun Min Choi; Young Wook Song

doi:10.4028/www.scientific.net/SSP.103-104.67

Paper Titles

Organic Contamination Control in Silicon Surface Processing
p.49

Application of UV/VIS-Spectroscopy for Determination of Complexing Agent Stability in APM and Like Mixtures Thereof
p.55

Plasma Cleaning for W Polymetal Gate
p.59

Development of New Batch-Type Plasma Assisted NOR (Native-Oxide-Removal) Dry Cleaning Equipment
p.63

Evaluation of Wafer Drying Methods for GIGA-LEVEL Device Fabrication
p.67

Surfactionated Rinse against Pattern Collapse and Defectivity in 193nm Lithography
p.71

Performance of a Linear Single Wafer IPA Vapour Based Drying System
p.75

Effective Rinse Aiming at Water-Mark-Free Drying for Single-Spin Wet Cleaning Process
p.79

Insights into Watermark Formation and Control
p.83

HomeSolid State PhenomenaSolid State Phenomena Vols. 103-104Evaluation of Wafer Drying Methods for GIGA-LEVEL...

Evaluation of Wafer Drying Methods for GIGA-LEVEL Device Fabrication

Abstract:

This study deals with drying induced water marks dependency on the last cleaning methods, substrate conditions, and drying pre-step delaying times, which are supposed to become a big issue with down scaling of device geometry. The data show that water marks induced by drying failure increase with increasing contact angle on the various surfaces. They are mainly composed of either silicon oxide only or silicon oxide with organic compounds. The former is removed by a dilute HF and/or hot SC-1 treatment and the latter is removed by organic removal cleaning followed by dilute HF etching.