Papers by Author: Anant K. Agarwal

Abstract: We report on specific features of forward voltage degradation of 4H-SiC p-i-n diodes in the pulse mode. It is shown that pulse stresses with a pulse duration shorter than several milliseconds cause substantially smaller forward voltage drift in comparison with a dc stress with the same charge passed through the diodes and the same distribution of injected carriers. A self-recovery of the forward voltage is observed at room temperature.

Abstract: In this paper we report the electrical and thermal performance characteristics of 1200 V, 100 A, 200°C (Tj), SiC MOSFET power modules configured in a dual-switch topology. Each switch-diode pair was populated by 2 x 56 mm2 SiC MOSFETs and 2 x 32 mm2 SiC junction barrier Schottky (JBS) diodes providing the 100 A rating at 200°C. Static and dynamic characterization, over rated temperature and power ranges, highlights the performance potential of this technology for highly efficient drive and power conversion applications. Electrical performance comparisons were also made between SiC power modules and equivalently rated and packaged IGBT modules. Even at a modest Tj=125°C, conduction and dynamic loss evaluation for 20kHz, Id=100A operation demonstrated a significant efficiency advantage (38-43%) over the IGBT components. Initial reliability data also illustrates the potential for SiC technology to provide robust performance in harsh environments.

Abstract: In this paper, very fast switch-off of high voltage 4H–SiC npn Bipolar Junction Transistors (BJTs) driven in deep saturation regime is reported. It is shown that the switch-off time can be as short as 4 ns if a reverse base current pulse is applied that provides forced minority carrier sweep out from the base.

Abstract: A novel power device configuration, the Bipolar Turn Off thyristor (BTO), was proposed and demonstrated in SiC. The BTO operates in anode switch configuration consisting of a 9 kV SiC p-type Gate Turn Off thyristor (GTO) and a 1600 V SiC n-type Bipolar Junction Transistor (BJT). Compared with SiC GTOs, several new features have been accomplished in the BTO: (1) A positive temperature coefficient of forward voltage drop, (2) Anode current saturation capability, and (3) A simple gate driver and fast switching speed.

Abstract: 4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

Abstract: In this paper, for the first time, we report a large area (1 cm2) SiC GTO with 9 kV blocking voltage fabricated on 100-mm 4H-SiC substrates with much reduced Basal Plane Dislocation (BPD) density. The static and dynamic characteristics are described. A forward drop of 3.7 V at 100 A (100 A/cm2) is measured at 25°C. A slight positive temperature coefficient of the forward drop is present at 300 A/cm2, indicating the possibility of paralleling multiple devices for higher current capability. The device exhibits extremely low leakage currents at high temperatures. The device has shown fast turn-on time of 53.9 nsec, and ~3.5 s of turn-off time, respectively. A stable forward voltage drop after electrical stress for >1000 hours has been achieved.

Abstract: We present physics based models for the occupation of interface traps and the mobility of the transition layer found in 4H-SiC MOSFETs and extract values for the same using combined numerical simulation and experimental characterization. The Si-C-O transition layer found in 4H-SiC MOS devices is electrically modeled as having a doping dependent mobility that is different from the regular bulk 4H-SiC bulk mobility. Compared to the high intrinsic bulk mobility of 4H-SiC, the transition layer intrinsic mobility was extracted to be approximately 165cm2/Vs. The occurrence of the excessive high density of interface traps near the conduction band edge led us to develop a new model for the occupation of traps lying inside the conduction band itself. Due to the conduction band trap densities being comparable to the conduction band electron states, a non-zero probability exists for their occupation, which causes the occupied trap densities to be very high in strong inversion. Detailed numerical simulations and corroboration with experiment have been performed to calibrate the models and extract physical parameter values.

Abstract: In this paper, we review the performance, reliability, and robustness of the current 4H-SiC power DMOSFETs. Due to advances in device and materials technology, high power, large area 4H-SiC power DMOSFETs (1200 V, 67 A and 3000 V, 30 A) can be fabricated with reasonable yields. The availability of large area devices has enabled the demonstration of the first MW class, all SiC power modules. Evaluations of 1200 V 4H-SiC DMOSFETs showed that the devices offer avalanche power exceeding those of commercially available silicon power MOSFETs, and have the sufficient short circuit robustness required in most motor drive applications. A recent TDDB study showed that the gate oxides in 4H-SiC MOSFETs have good reliability, with a 100-year lifetime at 375oC if Eox is limited to 3.9 MV/cm. Future work on MOS reliability should be focused on Vth shifts, instead of catastrophic failures of gate oxides.

Abstract: The influence of stacking fault (SF) generation on the reverse blocking characteristics has been investigated on SiC 10 kV, 5 A Merged PiN (MPS) diodes. For the first time, we have observed that the generation of SFs under forward biased stress increases the reverse leakage current. In addition, the presence of a secondary diode formed by the electrical stress was observed and attributed to the breakdown voltage failure on certain devices.

Abstract: Large area (8 mm x 7 mm) 1200 V 4H-SiC DMOSFETs with a specific on-resistance as low as 9 m•cm2 (at VGS = 20 V) able to conduct 60 A at a power dissipation of 200 W/cm2 are presented. On-resistance is fairly stable with temperature, increasing from 11.5 m•cm2 (at VGS = 15 V) at 25°C to 14 m•cm2 at 150°C. The DMOSFETs exhibit avalanche breakdown at 1600 V with the gate shorted to the source, although sub-breakdown leakage currents up to 50 A are observed at 1200 V and 200°C due to the threshold voltage lowering with temperature. When switched with a clamped inductive load circuit from 65 A conducting to 750 V blocking, the turn-on and turn-off energies at 150°C were less than 4.5 mJ.