Papers by Author: Bernd Thomas

Abstract: The paper describes first results of 6.5 kV SiC PiN diode modules which are designed as neutral point valves for medium-voltage power inverters rated for 1000 A. The power module consists of 4 AlN DCB substrates soldered on an AlSiC base plate. Each DCB is equipped with 20 SiC PiN diodes operating in parallel. The total active area of all 80 diode chips is 5.68 cm². At the rated current of 2 x 500A the forward voltage drops from 4.1 V at room temperature to 3.9 V at an averaged junction temperature of 125°C. The switching experiments show a very low reverse recovery charge of about 30 µC only. The conduction loss is comparable to the corresponding 6.5 kV silicon diode whereas the dynamic loss is marginal with respect to the forward conduction loss if the switching frequency is held below 10 kHz.

Abstract: Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.

Abstract: The paper compares static and dynamic characteristics of 6.5 kV SiC PiN diodes fabricated with different p-emitters. The version with the thickest p-emitter (4 µm) showed the lowest forward voltage (3.4 V at 100 A/cm²) and the lowest (negative) temperature coefficient. Forward voltage DC stress tests revealed a stability within the measurement error of the test apparatus (<50 mV). The dynamic performance showed a soft recovery even at 4 kV. The reverse recovery charge Qrr is analyzed for different forward currents and junction temperatures. The dynamic losses of the SiC PiN diode are marginal with view to the application in industrial inverters.

Abstract: Basal Plane Dislocations (BPDs) in SiC are thought to cause degradation of bipolar diodes with blocking voltages > 2kV by triggering the formation and expansion of stacking faults during device operation. Hence, low N doped, thick epitaxial layers without BPDs are urgently needed for the realization of long-term stable SiC bipolar diodes. Such epilayers can be achieved if the conversion of the BPD into another harmless dislocation type is supported by proper epitaxial growth parameters and use of vicinal (off-cut) substrates. In this work, the influence of the substrate’s off-cut angle and of the epilayer thickness on BPD density and surface morphology were investigated. The BPD densities of epilayers grown on 2° and 4° off-cut substrates were very low compared to growth on 8° off-axis substrates. X-Ray Topography has proved that all the Threading Dislocations (TD) propagate from the substrate to the epilayer and that BPDs in the substrate convert to Threading Edge Dislocations (TED) in the epilayer, i.e. the dislocation density (DD) of the substrate determines the epilayer’s DD. The conversion of BPDs is supported by the presence of bunched steps as for growth of thick layers on 2° and 4° off-cut substrates.

Abstract: In this paper, we present first results of epitaxial layer deposition using a novel warm-wall CVD multi-wafer system AIX 2800G4 WW from AIXTRON with a capability of processing 10x100mm wafers per run. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 10x100mm runs will be shown and compared to results of the 6x100mm setup of our hot-wall reactor VP2000HW by AIXTRON used for device production since 2001.

Abstract: 4H-SiC epilayers are homoepitaxially grown on 4H-SiC substrates with different C/Si-ratios and different growth rates by the chemical vapour deposition method. DLTS investigations are applied in order to trace energetically deep states of electrically active point defects and extended defects, which may act as the source for the degradation of electronic devices. In addition, the dependence of the DLTS signal heights on the filling pulse length is studied.

Abstract: Nitrogen doped 4H-SiC epitaxial layers grown by hot-wall chemical vapor deposition were investigated by deep level transient spectroscopy after irradiation with 6 MeV electrons or 1.6 MeV protons. The influence of silane and propane flows used during the epilayers growth on the behaviour of radiation induced EH6,7 levels is studied. Samples grown under different conditions were investigated: 1 sample grown in steps of different C/Si ratio obtained by changing the propane flow only; 1 sample grown in steps of different C/Si ratio obtained by changing the silane flow only; 2 samples grown with a C/Si ratio of 1.5 but with different flows of propane and silane. These investigations revealed that the low thermal stability of EH6,7 (the defects anneal out at temperatures as low as 750K) is due to the magnitude of silane flow used during the growth irrespective of the C/Si ratio. A possible structure of the EH6,7 defect is discussed.

Abstract: In this paper we present results on the growth of low-doped thick epitaxial layers on 4° off-oriented 4H-SiC using a commercially available hot-wall multi-wafer CVD system. For the first time we show results of a low-doped full-loaded 73” run on 4° off-oriented substrates with a layer thickness of more than 70 µm. The target doping concentration of 1.2×1015 cm-3 is suitable for blocking voltages > 6 kV. Results on doping, thickness and wafer-to-wafer homogeneities are shown. The surface quality of the grown layers was characterized by AFM. The density of different types of dislocations was determined by Defect Selective Etching.

Abstract: Basal Plane Dislocations (BPD) in SiC are thought to cause degradation of bipolar devices as they can trigger the formation and expansion of stacking faults during device operation. Therefore, epilayers without any BPD are strongly recommended for the achievement of long-term reliable bipolar devices. Such epilayers can be achieved by supporting the conversion of BPD into Threading Dislocations (TD), which depends on the epitaxial growth mode (as described in literature). In this work, the influence of several pre-treatments of the SiC substrate prior to epitaxial growth and different epitaxial growth parameters on the reduction of the BPDs in the SiC epilayers was investigated on 4° off-axis substrates. The dislocation content in substrates and epilayers was determined by Defect Selective Etching (DSE) in molten KOH. The averaged BPD density in epitaxial layers can be reduced to < 100 cm-2 for substrate preparation techniques and to < 30 cm-2 for well-suited epitaxial growth parameters. A certain combination of epitaxial growth parameters leads to < 3 BPD/cm2 in the epitaxial layer.

Abstract: In this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 7×3” or 6×100mm wafers per run in a new 100mm setup. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm and 7×3” runs will be shown. Results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3”, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.