Papers by Author: Fredrik Allerstam

Abstract: We investigate the strong passivation of shallow interface traps located near the SiC conduction band after enhanced oxidation of Si-face 4H-SiC in the presence of sodium. We find that removing the sodium ions present at the SiO2/SiC interface since oxidation by way of bias stress or annealing does not lead to a significant increase in the density of interface traps. The presence of sodium ions at the SiO2/SiC interface is therefore not responsible for the passivation of such interface traps in oxides formed by sodium enhanced oxidation.

Abstract: In this work the effect of oxidation temperature of 4H-SiC on the density of near-interface traps is studied. It is seen that the portion of traps with slower emission times decreases with increasing oxidation temperature. Despite this reduction, high temperature oxidation alone is not useful to achieve low density of interface traps at the SiO2/4H-SiC interface.

Abstract: This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage (BVCEO) of 1200 V, a maximum current gain (β) of 60 and the low on-resistance (Rsp_on)of 5.2 mΩcm2. The high gain is attributed to an improved surface passivation SiO2 layer which was grown in N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm × 1.8 mm showed a current gain of 53 in pulsed mode and a forward voltage drop of VCE=2V at IC=15 A (JC=460 A/cm2).

Abstract: Silicon Carbide MESFETs for microwave frequencies were made using a field-plated buried gate approach. The devices were fabricated using passivation oxides with different interface trap densities. By using a passivation oxide with a reduced interface trap density, grown in a sodium containing ambient, it was possible to achieve a very high continous wave output power density of the device: 8 W/mm at 3 GHz and 1 dB compression.

Abstract: This study is focused on characterization of deep energy-level interface traps formed during sodium enhanced oxidation of n-type Si face 4H-SiC. The traps are located 0.9 eV below the SiC conduction band edge as revealed by deep level transient spectroscopy. Furthermore these traps are passivated using post-metallization anneal at 400°C in forming gas ambient.

Abstract: The improvement of the SiC-SiO2 interface has been the main focus of research in SiC MOSFET technology due to the presence of high density of interface traps (Dit) leading to poor threshold voltage temperature stability and poor mobility. In SiC MOSFETs with the gate oxide grown in the presence of sodium, known as sodium enhanced oxidation(SEO), a lower Dit and higher field effect mobility has been observed [1]. Hall effect measurements were performed from 125°K-225°K on such MOSFET samples. The Hall measurements were made as a function of temperature for various sheet charge concentrations. The sheet charge density was measured as a function of gate bias at 225°K and there is very little trapped charge in the sample with oxide grown by SEO while about 50 % of the total charge is trapped in a sample with N2O grown oxide annealed in NO. In samples with oxide grown by SEO, there is a monotonic increase in mobility with sheet charge density and the mobility also increases with temperature. This is an indication that the main scattering mechanism is Coulomb scattering in this regime.

Abstract: We present new results on 4H-SiC RF power MOSFETs. By improvements in device layout we obtain better high frequency performance compared to the first generation of devices. An extrinsic transition frequency fT=11.4 GHz was achieved and fmax=11.2 GHz for a device with 0.5 µm nominal channel length. Functional devices with 0.3 µm nominal channel length were also made. These devices gave fT=15.1 GHz and fmax=19.5 GHz but they have lower breakdown voltages and therefore lower overall performance. The measured devices are double fingered with 0.8 mm total gate width.

Abstract: We demonstrate how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2/4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1-10 cm2/Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these nearinterface traps resulting in high inversion channel mobility of 150 cm2/Vs in such transistors. Sodium can be incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during formation of the SiC/SiO2 interface.

Abstract: We report investigations of MOS and MOSFET devices using a gate oxide grown in the presence of sintered alumina. In contrast to conventionally grown dry or wet oxides these oxides contain orders of magnitude lower density of near-interface traps at the SiO2/SiC interface. The reduction of interface traps is correlated with enhanced oxidation rate. The absence of near-interface traps makes possible fabrication of Si face 4H-SiC MOSFETs with peak field effect mobility of about 150 cm2/Vs. A clear correlation is observed between the field effect mobility in n-channel MOSFETs and the density of interface states near the SiC conduction band edge in n-type MOS capacitors. Stable operation of such normally-off 4H-SiC MOSFET transistors is observed from room temperature up to 150°C with positive threshold voltage shift less than 1 V. A small decrease in current with temperature up to 150°C is related to a decrease in the field effect mobility due to phonon scattering. However, the gate oxides contain sodium, which originates from the sintered alumina, resulting in severe device instabilities during negative gate bias stressing.