Papers by Author: Hiroshi Yano

Abstract: The sloped sidewall angle in 4H-SiC mesa structure could be controlled by a thermal etching at 900oC in chlorine (Cl2) based ambience. 4H-SiC C face with 8o off substrate was used. The SiO2 layers for the etching mask were formed by a deposited SiO2 layer or a thermally oxidized layer. Thermal etching was carried out at Cl2 ambience at 900oC for 15 minutes. The surface morphologies of the mesa structures were observed with the scanning electron microscope (SEM) and atomic force microscope (AFM). The sloped angles at the mesa sidewalls using deposited SiO2 mask and thermal SiO2 mask were about 23o and 60o, respectively. These results mean that the angle of sloped sidewall can change by mask fabrication method.

Abstract: Metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) were fabricated on C-face 4H-SiC with post-oxidation annealing in phosphorus- containing atmosphere. POCl3/N2 annealing at 1000 °C, which is an effective condition for Si-face, did not bring any improvement in the interface state density (Dit) for C-face due to additional oxide growth. We have developed a new process sequence suitable for C-face MOS structures. As a result, the Dit near the conduction band edge was drastically decreased by the developed process to less than 3x1011 cm−2eV−1. The field-effect mobility of C-face 4H-SiC MOSFETs was effectively increased to 37 cm2/Vs. We found that the incorporation of phosphorus atoms into the SiO2/SiC interface can improve MOSFET performance not only for the Si-face but also for the C-face.

Abstract: Surface properties of the 4H-SiC (0001) Si faces could be evaluated by the contact angle measurements with water droplet method, X-ray photoelectron spectroscopy and an atomic force microscope. The contact angles do not depend on the surface roughness under 3nm. The substrate surfaces with the contact angles over 30o will be terminated by hydrogen related species. The contact angles around 20o on 4H-SiC is caused by the removal of oxide layer with fluoride acid and terminated subsequently by the -CF species on the surface. The hydrophile surface of 4H-SiC is caused by the formation of chemical oxide layer as well as the case of the silicon wafers.

Abstract: We report on electrical and physical investigations aimed to clarify the mechanisms behind the high channel mobility of 4H-SiC metal–oxide–semiconductor field-effect transistors processed with POCl3 annealing. By low-temperature capacitance–voltage analysis, we found that the shallow interface traps are effectively removed by P incorporation. Using x-ray photoelectron spectroscopy, we found that the three-fold coordinated P atoms exist at the oxide/4H-SiC interface. The overall results suggest that P atoms directly remove the Si–Si bonds and thus eliminate the near-interface traps.

Abstract: . 　 Crystallographically specific pyramidal planes in 4H-SiC could be naturally formed at mesa sidewalls by a thermal etching at 900oC in a chlorine (Cl2) based ambience. The mesa structures have been fabricated on the 4H-SiC C-face with 0-45o off-angle toward [11-20]. The etched surface was rather smooth, and bunched step structures on the specific pyramidal planes were not observed with atomic force and scanning electron microscopes. The formation mechanisms of the specific pyramidal planes at mesa sidewalls are discussed on the basis of these experimental results.

Abstract: Thermal etching of hexagonal (4H-, 6H-, 8H- and 10H-), rhombohedral (15R- and 21R-), and cubic (3C-) SiC Si-faces was performed between 900 and 1000oC in a mixed gas of chlorine (Cl2) and oxygen (O2). In the case of well oriented Si-faces, the 3C-SiC (111) substrate was etched fastest in polytypes. The etching rate in the dislocation-free area depended on the hexagonality. Etch pits with definite shapes appeared, which depend on the type of dislocation and crystal structures. On the basis of these results, etching properties are discussed.

Abstract: Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.

Abstract: We have investigated NH3 plasma pretreatment for Si- and C-face 4H-SiC and characterized interface properties and bond configuration. It is revealed that the NH3 plasma pretreatment is effective to reduce interface state density on C-face. From X-ray photoelectron spectroscopy (XPS) measurements, N- and H-related C bonds were observed. N and H passivate C-related defects and dangling bonds, resulting in improved interface properties.

Abstract: A change in the interface state density in 4H-SiC metal–oxide–semiconductor (MOS) structures by incorporation of various elements was systematically investigated. B, N, F, Al, P, and Cl ions were implanted prior to the oxidation and introduced at the SiO2/SiC interface by subsequent thermal oxidation. Interface state density near the conduction band edge for Al-, B-, F-, and Cl-implanted MOS capacitors increased with implantation dose. On the other hand, a strong reduction of the interface state density was observed for N- and P-implanted samples when the implantation dose was larger than 5.0 × 1012 cm−2. It was found that the interface state density can be reduced by P as well as N.

Abstract: This paper describes the influence of the geometric component in the charge-pumping measurement of 4H-SiC MOSFETs. Charge-pumping measurements were conducted on 4H-SiC MOSFETs with and without NO annealing. Charge-pumping measurements with different pulse-fall times revealed that the geometric component exists in 4H-SiC MOSFETs and is especially large in the unannealed MOSFETs. A sufficiently long fall-time is needed to minimize its effect, which is expected to be 1–10 μs for 4H-SiC MOSFETs with a gate length of 10 μm.