Papers by Author: Igor Sankin

Abstract: The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

Abstract: SiC Lateral Trench JFET (LTJFET) technology is demonstrated as a promising candidate for use in high-temperature wireless telemetry systems. 4H-SiC LTJFETs were designed, fabricated and characterized for DC, and small-signal AC and RF performance at different case temperatures. Four-fold drain current reduction was observed at 460°C as compared to RT measurements. The measured threshold voltage shift was less than 2.3 mV/°C from 21°C to 460°C. A simple common source amplifier built using a fabricated device demonstrated stable small-signal AC performance after 100 hrs of operation at 450°C. Small-signal RF measurements were carried out on the packaged devices at different temperatures. GMax above 8 dB was measured over the L-band frequency range at RT. The average degradation of small-signal power gain measured at f=250 MHz did not exceed 0.0125 dB/ °C over the temperature ranging from 21°C to 365°C.

Abstract: In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

Abstract: Epitaxial growth of 3-in, 4° off-axis 4H SiC with addition of HCl has been presented. Good surface morphology with a low defect density has been obtained, even for epi thickness of 38 µm. Comprehensive characterization techniques conducted on the epi material obtained in this process have independently confirmed the high purity and low density of crystalline imperfections. Low temperature PL displays clear free exciton I77 recombination while no L1 line is discernable. DLTS measurements have confirmed a low concentration of Z1/2 and EH6/7 below or in the range of 1011 cm-3. Time resolved PL at room temperature performed on a 38 µm thick epi wafer gives long carrier lifetime in the range of 1.5 to above 5 µsec. PiN diodes with diode area up to 25 mm2 have demonstrated blocking voltages above 900V, with a max electric field of above 2.5 MV/cm.

Abstract: In this paper we present highly uniform SiC epitaxy in a horizontal hot-wall CVD reactor with wafer rotation. Epilayers with excellent thickness uniformity of better than 1% and doping uniformity better than 5% are obtained on 3-in, 4° off-axis substrates. The same growth conditions for uniform epitaxy also generate smooth surface morphology for the 4° epiwafers. Well controlled doping for both n- and p-type epilayers is obtained. Abrupt interface transition between n- and pdoped layers in a wide doping range is demonstrated. Tight process control for both thickness and doping is evidenced by the data collected from the epi operations. The average deviation from target is 2.5% for thickness and 6% for doping. PiN diodes fabricated on a standard 3-in, 4° epiwafer have shown impressive performance. More than half of the 1 mm2 devices block 1 kV (2.3 MV/cm) with a low leakage current of 1 μA.

Abstract: Dielectric charges and charge stability were compared in different dielectrics formed on SiC by different processing techniques. The concentration and transient behavior of the interface and trapped charges were investigated. Strong hysteresis and flat-band voltage drift under applied bias were observed in some of the samples. They are attributed to the trapping of the charge injected in the dielectrics. Differences in charge injection, charge trapping, and capture/emission of carriers by interface traps were pronounced for the investigated SiO2 and Si3N4 dielectrics.

Abstract: Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a self-aligned fabrication process. The self-aligned fabrication process required no critical alignments and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull measurements were taken with the devices externally matched. Devices having the narrowest finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2 dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate to power densities of 22 kW/cm2.

Abstract: Wide bandgap semiconductor materials such as SiC or GaN are very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. Monolithic or hybrid integration of a power transistor and control circuitry in a single or multi-chip wide bandgap power semiconductor module is highly desirable for such applications in order to improve the efficiency and reliability. This paper describes a new monolithic SiC JFET IC technology for high-temperature smart power applications that allows for on-chip integration of control circuitry and normally-off power switch. In order to demonstrate the feasibility of this technology, hybrid logic gates with maximum switching frequency > 20 MHz and normally-off 900 V power switch have been fabricated on alumina substrates using discrete enhanced and depletion mode vertical trench JFETs.

Abstract: In this work we have demonstrated the operation of 600-V class 4H-SiC vertical-channel junction field-effect transistors (VJFETs) with 6.6-ns rise time, 7.6-ns fall time, 4.8-ns turn-on and 5.4-ns turn-off delay time at 2.5 A drain current (IDS), which corresponds to a maximum switching frequency of 41 MHz – the fastest ever reported switching of SiC JFETs to our knowledge. At IDS of 12 A, a 19.1 MHz maximum switching frequency has been also achieved. Specific on-resistance (Rsp-on) in the linear region is 2.5 m
·cm2 at VGS of 3 V. The drain current density is greater than 1410 A/cm2 at 9 V drain voltage. High-temperature operation of the 4H-SiC VJFETs has also been investigated at temperatures from 25 °C to 225 °C. Changes in the on-resistance with temperature are in the range of 0.90~1.33%/°C at zero gate bias and IDS of 50 mA. The threshold voltage becomes more negative with a negative shift of 0.096~0.105%/°C with increasing temperature.

Abstract: 4H-SiC vertical depletion-mode trench JFETs were fabricated, packaged, and then irradiated with either 6.8 Mrad gamma from a 60Co source, a 9x1011 cm-2 dose of 4 MeV protons, or a 5x1013 cm-2 dose of 63 MeV protons. 4H-SiC Schottky diodes were also fabricated, packaged and exposed to the same irradiations. The trench VJFETs have a nominal blocking voltage of 600 V and a forward current rating of 2 A prior to irradiation. On-state and blocking I-V characteristics were measured after irradiation and compared to the pre-irradiation performance. Devices irradiated with 4 MeV proton and gamma radiation showed a slight increase in on resistance and a decrease in leakage current in blocking mode. Devices irradiated with 63 MeV protons, however, showed a dramatic decrease in forward current. DLTS measurements were performed, and the results of these measurements will be discussed as well.