Papers by Author: Makoto Kato

Abstract: 3kV UMOSFET with buried p-base regions was developed to realize the low on-resistance with low electric field in the gate oxide for off-state. The buried p-base region was formed simultaneously with the p-base region by utilizing MeV ion implantation. Influence by the structural parameter such as cell geometry and space between the buried p-base region and the trench gate was investigated. The hexagonal cell with high channel density exhibits an extremely low on-resistance of 6.8 mΩcm² with threshold voltage of 5.0 V at room temperature.

Abstract: UMOSFET is theoretically suitable to decrease the on-resistance of the MOSFET. In this study, in order to determine the cell structure of the SiC UMOSFET with extremely low on-resistance, influences of the orientation of the trench and the off-angle of the wafer on the MOS properties are investigated. The channel resistance, gate I-V curves and instability of threshold voltage are superior on the {11-20} planes as compared with other planes. On the vicinal off wafer, influence of the off-angle disappears and the properties on the equivalent planes are almost the same. The obtained results indicate that the extremely low on-resistance with the high stability and high reliability is possible in the SiC UMOSFET by the hexagonal cell composed of the six {11-20} planes on the vicinal off wafer, and actually an extremely low channel resistance was demonstrated on the hexagonal UMOSFET with the six {11-20} planes on the vicinal off wafer.

Abstract: Reliability of the gate oxide is influenced by the device structure and the processes. In the SiC MOSFET, the surface morphology is degraded by the high temperature activation RTA, and the degradation is remarkable on the n+ source region. This study develops the method to suppress the degradation of the reliability of the gate oxide on the carbon face. By utilizing the carbon cap for the RTA and the high density O2 plasma etching to remove the carbon cap, the reliability is drastically improved both on the un-implanted and the implanted surfaces. Especially, the degradation of the reliability is perfectly suppressed on the un-implanted surface.

Abstract: The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm2 and excellent dynamic characteristics.

Abstract: 4H-SiC MOSFET on carbon face exhibits the high channel mobility when the gate oxide is formed by pyrogenic wet oxidation. However, this improvement is not proof against the metallization annealing which is indispensable in the fabrication of the SiC power MOSFETs. We develop the alternative metallization process suitable for the high channel mobility on the carbon face. The metallization annealing in hydrogen ambient has much effect to suppress the degradation of the channel mobility. The lateral MOSFET with the ohmic contact formed by hydrogen annealing exhibits the high channel mobility which is comparable to the channel mobility of the lateral MOSFET formed without metallization annealing.

Abstract: SiC power MOSFETs are expected to be normally-off type fast switching devices. The on-resistance of SiC power MOSFETs is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface state density (Dit). We have already reported that 4H-SiC MOSFETs on the C(0001 _ ) face had higher inversion-channel mobility. However, there is the SiO2/SiC interface roughness problem in SiC MOSFETs. There are many steps at the SiO2/SiC interface because a high off-angle is necessary for SiC epitaxial growth. These steps might make SiO2/SiC interfaces rough, which leads to reduction of channel mobility. In this work, we have investigated the effect of the SiO2/SiC interface roughness caused by the off-angle on the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(0001 _ ) face. The inversion-channel mobility of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the vicinal off-angle(0.8°) is higher than that of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the 8° off-angle. Reduction of the off-angle is very useful for improvement of channel mobility. A C(0001 _ ) epitaxial substrate with the vicinal off-angle would be suitable for SiC DMOSFETs.

Abstract: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 m
cm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 m
cm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.

Abstract: This paper reports on the degradation of inversion channel mobility of SiC MOSFET caused by the increase of channel doping. SiC MOSFETs were fabricated on three wafers, the doping concentrations of the epitaxial layer of which were 16 10 2× cm-3 (sample A), 17 10 2× cm-3 (sample B) and 17 10 4× cm-3 (sample C). The field effect mobility sharply decreases as the doping concentration increases. Hall mobility measurements have been done to investigate the degradation of the mobility due to doping. The measurement of sample A shows that, as a consequence of the decrease of the free carrier density due to MOS interface traps, the Hall mobility is as much as a factor of ten higher than the field effect mobility. In contrast, in regard to the measurement of sample B and sample C, we encountered unstable Hall voltage and could not obtain reproducible results. This implies that such high-density traps are generated that a channel disappears in the higher-doping samples.

Abstract: We have fabricated lateral RESURF MOSFETs on 4H-SiC(0001) Si-face and (000-1) C-face substrates, and compared those properties. The channel mobility of a lateral test MOSFET on a C-face was 41 cm2/Vs, which was much higher than 5 cm2/Vs for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was improved to 79 mΩcm2 as comparison with 2400 mΩcm2 for Si-face. The breakdown voltage was 490V for Si-face and 460V for C-face, which was 82% and 79% of the designed breakdown voltage of 600V, respectively. The device breakdown occurred destructively at the gate electrode edge.