Papers by Author: Michael G. Spencer

Abstract: A betavoltaic cell in 4H SiC is demonstrated. An abrupt p-n diode structure was used to collect the charge from a 1mCi Ni-63 source. An open circuit voltage of 0.95V and a short circuit current density of 8.8 nA/cm2 were measured in a single p-n junction. An efficiency of 3.7% was obtained. A simple photovoltaic type model was used to explain the results. Good correspondence with the model was obtained. Fill factor and backscattering effects were included. Efficiency was limited by edge recombination and poor fill factor.

Abstract: A new silicon carbide (SiC) enhancement-mode lateral channel vertical junction fieldeffect transistor (LC-VJFET), namely “source inserted double-gate structure (SID-gate) with a supplementary highly doped region (SHDR)”, was proposed for achieving extremely low power losses in high power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LCVJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20 % reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75 % ~ 95 % reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.

Abstract: Because SiC does not have velocity overshooting behaviour, the current density of SiC metal-semiconductor field-effect transistors (MESFETs) is restricted by low drift velocity in the parasitic region between source and gate where the applied electric field is low. In addition, the extension of the depletion region toward the drain side at high drain voltages increases the effective channel length and, as a result, lowers the cut-off frequency due to the increased transit time.