Papers by Author: T. Paul Chow

Abstract: This paper presents a study of performance and scalability of 8kV SiC PIN diodes focusing on area-dependent yield and sensitivity to material properties variation. Successfully fabricated 18 and 36 mm2 SiC-PiN diodes exhibited avalanche breakdown above 8 kV and < 5V forward voltage drop at 100 A/cm2 current density. The fast switching operation of these diodes up to ~5 kHz frequency is evidenced by reverse recovery measurements with by double-pulse inductive switching tests. The devices exhibit 0.142 and 0.169 uC/cm2 stored charge at room temperature and 125oC, respectively, when turned-off from Jf = 100A/cm2 to Vr = 2.1 kV. The measured diode breakdown voltage exhibited location and size dependent yield, indicating the necessity of material quality improvements for production.

Abstract: The effect of using two different polytypes, 4H-SiC and 6H-SiC, on the performance of (0001) SiC MOSFETs has been studied. 4H-SiC and 6H-SiC MOSFETs have been fabricated with deposited gate oxides followed by oxidation in dry O2 or NO. Device parameters, particularly field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. We have also compared the mobility-limiting mechanisms of (0001) 4H and 6H-SiC MOSFETs and found that inversion mobility can be further improved in 4H-SiC, but not 6H-SiC.

Abstract: To study the mobility limiting mechanisms in (0001) 4H-SiC and 6H-SiC MOSFETs, physics based modeling of the inversion mobility of has been done. Two very different limiting mechanisms have been found for 4H-SiC and 6H-SiC MOSFETs. The mobility in 6H-SiC MOSFETs is limited by phonon scattering while the 4H-SiC MOSFET mobility is limited by Coulombic at low electric fields and surface roughness scattering at high electric fields.

Abstract: High temperature C-V characterization with and without UV illumination has been performed on n-type 4H-SiC MOS capacitors fabricated using different processing conditions to extract various types of interfacial charges. An anomalous positive flatband voltage shift with temperature has been observed in most of the SiC MOS capacitors measured. We have experimentally identified an extra type of fixed charges at the 4H-SiC/SiO2 interface from the temperature dependence of the flatband voltage, particularly under UV illumination.

Abstract: We have comparatively characterized the electrical characteristics of 4H-SiC and 2H-GaN MOS capacitors and FETs. While progressive refinement of gate oxide processes, notably with NO anneal, has resulted in better threshold voltage control, reduced subthreshold slope and higher field-effect mobility for 4H-SiC MOSFETs, we have recently reported more superior MOS parameters for 2H-GaN MOSFETs. In addition, we have performed MOS-gated Hall measurements to extract the intrinsic carrier concentration and MOS mobility, indicating that both less channel electron trapping and scattering take place in 2H-GaN MOSFETs.

Abstract: The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.

Abstract: The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

Abstract: GaN MOS capacitors were characterized to optimize the electric properties of SiO2/GaN interface. With optimized anneal conditions, an interface state density of 3.8×1010/cm2-eV was estimated at 0.19 eV near the conduction band and decreases deeper into the band gap. Enhancement-mode GaN MOSFETs were experimentally demonstrated on both p and n GaN epilayer with record high field-effect mobility of 167 cm2/V-s. Lateral RESURF-type GaN MOSFETs exhibit non-destructive high voltage (up to 940V) blocking capabilities. Other characterization including mobility orientation dependence, MOS-gated Hall mobility, current collapse and an NMOS inverter utilizing E/D mode GaN MOSFETs have also been experimentally demonstrated.

Abstract: The impact of anode layers on the electrical characteristics of 10kV 4H-SiC PiN diodes has been evaluated in this work. Co-fabricated diodes with various epitaxial anode layer designs as well as those employing P+ implanted injecting layers are used to experimentally investigate the device conduction mechanisms. The role of the injecting layer is demonstrated via electrical characteristics and numerical simulations, showing the importance of maintaining sufficient carrier recombination lifetime in the device anode region.

Abstract: The effect of incorporation of cesium with implantation on the electrical characteristics of SiO2/4H-SiC interface has been evaluated using MOS capacitors. With a cesium dosage of 1012 and 3x1012 cm-2 on deposited oxide re-oxidized in steam, effective oxide charge densities of - 1.4x1012 and -7.5x1011 cm-2 respectively were extracted and a cesium implant activation percentage of 33% was estimated from flatband voltage shift. Also, corresponding interfacial state densities of 2.5x1013 and 1.8x1013 cm-2-eV-1 near the conduction band edge were extracted from High-Low frequency C-V technique, showing a decreasing Dit with increasing Cs dosage.