Papers by Keyword: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

Abstract: This paper reports the channel mobilities of MOSFETs formed on the trench sidewalls with different crystal faces including (0001), (000-1), (1-100) and (0-33-8) using 4H-SiC (11-20) substrates. Deposited poly-Si was oxidized in wet ambient to form the gate oxide, and annealed in N2O (10%) ambient. The order of drain current of trench sidewall MOSFETs was (0-33-8) > (1-100) > (000-1) = (0001). We could gain comparatively high channel mobility on the (0-33-8) face. The maximum effective channel mobility (μeff) was 35cm2/Vs, and μeff at 2.5MV/cm was 29 cm2/Vs on the (0-33-8) face.

Abstract: Prototype SiC power modules are fabricated using our class 10 A, 1.2 kV SiC-MOSFETs and SiC-SBDs, and their switching characteristics are evaluated using a double pulse method. Switching waveforms show that both overshoot and tail current, which induce power losses, are suppressed markedly compared with conventional Si-IGBT modules with similar ratings. The total switching loss (MOSFET turn-ON loss, turn-OFF loss and SBD recovery loss) of SiC power modules is measured to be about 30% of that of Si-IGBT modules under the generally-used switching condition (di/dt ~250A/μs). The three losses of SiC modules decrease monotonically with a decrease in gate resistance, namely switching speed. The result shows the potential of unipolar device SiC power modules.

Abstract: 4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer channel which improves the surface where the MOS channel is formed. By the optimization of the epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 m
cm2 is obtained at VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage increase slightly with an increase in temperature. This behavior is favorable for high power operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length and it corresponds to an effective channel mobility of about 20 cm2/Vs.

Abstract: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 m
cm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 m
cm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.

Abstract: We describe an optimized design for the 1 kV short-channel 4H-SiC power DMOSFET, obtained from numerical simulations using the Taguchi method. Three new structural features are employed: (1) a current spreading layer (CSL) below the p-well, (2) a heavily-doped, narrow JFET region, and (3) a segmented p-well contact.

Abstract: Depletion-mode 4H-SiC FETs were fabricated for use as harsh environment gas sensors. To enable sensitivity to NOx, O2 and H2 gases, metal oxide catalysts such as InOx were integrated into the gate of the device. The FETs had a total area of approximately 1 mm2. Devices with various gate widths and lengths were fabricated and tested, with sensor performance of 5% or greater in current change from the baseline resulting from designs having a length to width ratio of around 50.

Abstract: We compare the on-state characteristics of five 4H-SiC power devices designed to block 20 kV. At such a high blocking voltage, the on-state current density depends heavily on the degree of conductivity modulation in the drift region, making the IGBT and thyristor attractive devices for high blocking voltages.

Abstract: This paper reports on a 400 watt boost converter using a SiC BJT and a SiC MOSFET as the switch and a 6 Amp and a 50 Amp SiC Schottky diode as the output rectifier. The converter was operated at 100 kHz with an input voltage of 200 volts DC and an output voltage of 400 volts DC. The efficiency was tested with an output loaded from 50 watts to 400 watts at baseplate temperatures of 25°C, 100°C, 150°C and 200°C. The results show the converter in all cases capable of operating at temperatures beyond the range possible with silicon power devices. While the converter efficiency was excellent in all cases, the SiC MOSFET and 6 Amp Schottky diode had the highest efficiency. Since the losses in a boost converter are dominated by the switching losses and the switching losses of the SiC devices are unaffected by temperature, the efficiency of the converter was effectively unchanged as a function of temperature.

Abstract: A new technique that reduces stacking fault (SF) density in 3C-SiC, termed switch-back epitaxy (SBE), is demonstrated regarding its effects on morphological and electrical properties. SBE is a homoepitaxial growth process on backside of 3C-SiC grown on undulant-Si. The key feature of SBE, the surface polarity of residual SFs in 3C-SiC, which cannot be erased by heteroepitaxial growth on undulant-Si, is converted from the Si-face to the C-face. The SF density on the surface of 3C-SiC grown by SBE shows a remarkable decrease to one-seventh lower than that on undulant- Si. The leakage current of pn-diode epitaxially fabricated on the 3C-SiC substrate grown by SBE decreases to as low as one-thirtieth that on 3C-SiC substrate grown without SBE. These results suggest that SBE eliminates the SFs on the surface of 3C-SiC and subsequently reduces the leakage current at pn-junction thus fabricated.

Abstract: The use of semiconductor materials in radiation processing, radiation therapy and diagnostics, and detection of cosmic radiation motivated development of numerical methods for its radiological characterization. This paper presents the application of the Monte Carlo method using the FOTELP-2K4 code for radiological characterization of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) dosimeter. The advantages of MOSFET dosimeters include small size, immediate readout, and ease of use for a wide photon energy range. In order to determine the dosimeter response accurately, distribution of the absorbed dose in the MOSFET structure has been investigated. Our results show that the absorbed dose distribution calculated by the presented simulation model compares well with the published data.